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6T SRAM

ABHISEK SINGH

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Hey FOLKS, can anyone assist me with performing READ, WRITE and DELAY of a 6T-SRAM cell in CADENCE VIRTUOSO 45nm CMOS technology.
I designed below test schematic and generated HSPICE netlist but confuse in how to modify the netlist in order to perform READ, WRITE and DELAY operations.

Kindly assist here.
 

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