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Recent content by cdic

  1. cdic

    DFT - are there any ways to improve fault coverage?

    Pay more attention to the interface to the macros, memories etc... Those can easily decrease your coverage. Always generate the bist wrapper for memories with bypass mode implemented.
  2. cdic

    jtag in P&R phase - what I should pay attention to

    Re: jtag in P&R phase place them close to each digital "jtaged" pad. Just standard cells, some of the companies make it a small macro.
  3. cdic

    how to specify internal net as scanmode signal

    set_dft_drc_configuration -internal_pins enable
  4. cdic

    TSMC - 40 nm tech - Synchronizer cell

    synchronizer cell No, actually there are no such need, you just form yours.
  5. cdic

    Will metal fill or dummy metal be fabricated at foundry

    Re: Will metal fill or dummy metal be fabricated at found It's all about your yield, foundry is just foundry, if you want, you can ask them to manufacture a PG short gds, as long as you pay for it. I used to tapeout a design with thousands of antenna violations to meet the TTM.
  6. cdic

    What is major difference between Magma Blast and Talus ?

    Re: Magma Blast and Talus Talus was branched out from Blast during the law suit between M@gm@ and syn0psys several years ago, It's M@gm@'s back-up just in case, after years, all the enhancement, later on development went into T@lus, and some went into Bl@st, and m@gm@ intended to give-up Bl@st...
  7. cdic

    STA of Astro is the same as STA of prime time

    Actually the timing engineer inside the PT and Astro is totally different, but any of the Astro release you are using is at least 92% correlated with PT(Synopsys internally will pass large amount of regression test cases before releasing, 92% is the number that they have to pass). If you want to...
  8. cdic

    what is the effect to chip if latency is high!

    Depends on your reset stratedgy and reset circuit. Long latency won't slow down your chip speed, but it will slow down your chip interface timing in general. If you move to 90/65nm, long clock latency is critical to your design, you need to make it as short as possible. actually it's a quite...
  9. cdic

    Which P&r tool will get better result?

    PC+Astro > BlastFusion > SoCEncounter in terms of overall QoR, but Nanoroute is the best router in the world! IC Compiler did better job than PC+Astro in our test cases. Talus is under evaluation, no data. If you are looking for performance, budget is not your concern, go for Synopsys, stable...
  10. cdic

    case sensitivity in LVS

    calibre lvs case sensitive If in your design, you have net "A" and "a" which are different nets logically, than you need to turn on the case sensitive on(That is the bad design style, you should avoid it). other-wise, turn off the case sensitive. go back to your questions, if your design has...
  11. cdic

    Magma tool information

    SoCEncouter is the worst PHysical implementation tool(except for routing) among the 3 eda vendors(cadence, synopsys, magma). As to the semicustom design, it depends your design scope and flow, magma is very flexable, but layout editing is a big con. The biggest advantage you can get from the...
  12. cdic

    Lithography process and illumination schemes in the microchip manufacturing process

    Re: lithography check with clear-shape website or magma website, it's hot topic for 90/65nm now.
  13. cdic

    Top-block layout clean in LVS calibre but not in Hercules...

    Re: Top-block layout clean in LVS calibre but not in Hercule Oh, I see. Then it must because of the pin swap, there are some options you can set in both calibre and hercules to ignore it.
  14. cdic

    Top-block layout clean in LVS calibre but not in Hercules...

    layout clean you sure logic is different? or just property error?
  15. cdic

    astro using help!

    remove *.lock in the astro library directory.

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