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Could someone tell me suitable basic Linux commands for all the 3 situations below?
1) Warm reboot, that only asserts a reset signal on the motherboard, while the power is not going away even for a fraction of a second, then the system starts up again. It is RST_CPU (with SYS_RST=1) in the CF9...
What is the difference between (inside a clocked statemachine):
and
I intuitively think the first one synthesizes an adder logic block with long timing path, the second one calculates yy-1 during compilation and creates a new constant.
How does the extra delay affect the state machine...
There is a feature that some of the DC/DC converters have, that is to discharge the output capacitors (by the lower mosfet) when the converter is not enabled (by the enable input pin). The most common step down DC/DC (buck) converter architecture is called "synchronous rectifier", this basically...
Have you seen a QFN footprint with absolutely zero soldermask under the qfn package? The package body is a massive rectangle opening on the soldermask layer.
Someone was showing me this, and the purpose was to allow flux to exit from under the center pad.
But with no soldermask coverage...
Do you guys rely on post layout si simulations to validate designs?
Specifically for 10gig serial links.
I have seen 2 approaches:
One is the si team does nothing else but extracting board files and compare eye diagrams against eye mask.
The other one is only do si what if analysis at early...
Hi,
Is there any difference in backdrilling rules between class 2 and 3 ?
Backdrilling rules like:
- BD tool diameter
- BD tool to circuit clearance (trace of plane void edge)
- via drill size to BD tool oversize
Regards,
Istvan
I have a sump pump (AC motor) that I cannot physically access every day.
I need to monitor it's health. The only thing I can do is to monitor when it runs (logs) and how much current it draws, over wifi from a $10 Emporia smart outlet.
It normally runs for a few minutes and draws 8A current...
From what I have read, the new core still provides the full TLP, but adds an AXI header to it. The TRN provided only raw data.
When a pcie packet arrives, and I get a TLP on axi, possibly I can reject it. But for read requests, I have to generate a completion packet and assemble an additional...
What's the difference between TRN and AXI4-Stream interfaces?
I implemented a PCI-express transaction layer logic that worked on the Spartan-6 device. The PCIe endpoint IP had a TRN interface that simply passed the TLP packet to the user logic, my user logic that decoded the TLPs for generating...
What I was trying to do is to make a channel model that i can change easily.
Instead of 3 parts per tline each with lots of parameters, I would have one tline with few parameters (length, imp, loss). Just like in ADS.
I am using coupled nonlossy lines with a equation device to add the loss to...
Thanks.
Is there a connector that has multiple coax signals in a group in a rectangular fashion?
How bad is the digital array connector for RF signals? Noise, crosstalk... I mean for high level 1Vpp, not the antenna signals that are like -100dBm.
Actually I built a model in QUCS. 2 half length transmission lines, and an RF equation device in between with the transmission equations being K*DF*f/f0.
Not sure if it's correct modelling.
I cannot put this into a subcircuit, due to a bug in QUCS causing error. So I have to copy over a block of...
RF analog signals through stacking board-to-board connectors.
Is this a "no-no".
I am thinking on a project with a 2Gs/s AD converter, a digital board with FPGA and an analog RF daughtercard. For best signal quality the high speed AD converter would be on the daughter card with the RF circuits...
I want to generate an s-parameter output and display of a complete channel. One of the several elements in the channel is a transmission line with user controlled parameters (length, loss, impedance).
I know ADS is better, but I was trying to make a complete simulation flow using free software.
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