Difference between if xx+1=yy then and if xx=yy-1 then

[buenos]

What is the difference between (inside a clocked statemachine):

if (xx+1=CONST1) then
state <= STATE1;

and

if (xx=CONST1-1) then
state <= STATE1;

I intuitively think the first one synthesizes an adder logic block with long timing path, the second one calculates yy-1 during compilation and creates a new constant.
How does the extra delay affect the state machine transition? Static timing wise?
Can it cause the state machine to jump to random states due to the adder logic's carryover delays?

 

[kaz1]

If compiler is reasonably clever it will decide to adjust +1/-1 either way at compile time. If it is
"stupid" then it will create adder but timing has to pass in any case. If so it is just a burden on timing.

 

[FvM]

If the design passed timing analysis, no problems expectable.

 

[dpaul]

I intuitively think the first one synthesizes an adder logic block with long timing path, the second one calculates yy-1 during compilation and creates a new constant.

You do not assume things, you must open the synthesized design in both cases and check!

Having said that, it is too small a problem to spend time upon for engineers who are working on huge design. An engineer will just have the RTL coded in any of the above two ways and proceed to timing analysis. Only if the design fails timing then one needs to go back and look in to the RTL.
So from a personal point of view, even during design reviews, such things are ignored.

 

[ads-ee]

The first version with xx+1 (depending on the width of xx and assuming it is not a constant) will result in a adder followed by a comparison, in all synthesis tools I've used, i.e.: Intel, Xilinx, ISE, and Synplify Pro. It will probably do the same in any other synthesis tool.

Using variables for counters can exhibit a similar issue with adders being placed after the registers and the resulting xx+1 being used in other combinational logic. I posted an example of this synthesis behavior on edaboard many years ago.

The second version will result in the variable xx being compared to a constant, which will result in a much smaller faster circuit. Comparisons to constants are efficiently implemented in an FPGA.

Regardless what others claim I would note code like "xx+1 = CONST" in a review unless the clock being used was slow relative the the maximum frequency of the FPGA technology. IMO it is better to design for speed if you need it instead of finding out later that you need to fix code like this because you didn't account for how the logic is synthesized. This is why I cringe everytime I have to pick up a design by another engineer, in my experience most engineers write code with complete disregard to the size of the logic cones between registers. I've found that this typically renders the design highly unstable to changes as even the smallest change (modifying a constant) can have dramatic results on timing closure, I've also noticed that the majority of those same engineers have to turn on whatever options that may exist for "register retiming" to have any chance of close timing.

 

[FvM]

The first version with xx+1 (depending on the width of xx and assuming it is not a constant) will result in a adder followed by a comparison, in all synthesis tools I've used, i.e.: Intel, Xilinx, ISE, and Synplify Pro. It will probably do the same in any other synthesis tool.

With Intel Quartus, I see an adder in RTL netlist, but it's actually synthesized as a simple compare operation.

    process (clk)
      begin
        if rising_edge(clk) then
            if num + 1 = 7 then
                res <= '1';
            else
                res <= '0';
            end if;
        end if;
      end process;