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DCDC chip feature to discharge the output

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Advanced Member level 3
Oct 24, 2005
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There is a feature that some of the DC/DC converters have, that is to discharge the output capacitors (by the lower mosfet) when the converter is not enabled (by the enable input pin). The most common step down DC/DC (buck) converter architecture is called "synchronous rectifier", this basically has an upper mosfet (drives to VDD) and a lower mosfet (drives to GND) connected to the output inductor. The lower of the 2 mosfets is utilized by some controllers to short the output to ground before the enable is asserted (before turn on event), and after the enable is de-asserted (after a turn off event).
Some controllers seem to have this feature, while others don't. I can tell when the basic controller is turned off, its output voltage slowly decays, instead of shutting off, some cases even worse the output decays to a plateau, stays there, then decays further. The intermediate voltage can cause digital chips to malfunction, so a decisive shutdown is preferred. It can fool reset generators to de-assert an internal reset signal before VCC would become stable enough.
Years ago I saw this described in detail in a DCDC controller chip datasheet. Today I looked at some datasheets and I found no reference to whether they have it or not.

So, my question is: what is this feature called? How to find out about each new DCDC chip datasheet whether they have this feature or not.


I never have encountered the described problem.
A hard switched ON low side Mosfet may cause very high current to discharge the output capacitor. It may even damage the capacitor.

--> Please post part numbers of the SMPS controller ICs, so that we can verify the bahavior.

It can fool reset generators to de-assert an internal reset signal before VCC would become stable enough.
I doubt this. It's the job of a reset generator to generate a reset in case of invalid VCC.
If it can be "fooled" it is no good reset generator.

--> Please post part numbers and voltage situations (diagram, sketch) with the problematic voltage levels, so we can verify this.


I don't know what it is called by others. But I know why we
elected to make our buck POL's output go hi-Z rather than
shunting when disabled - we wanted to enable "hot-spare
redundancy" (N+K) meaning that you could attach a disabled,
powered buck of the same type to a common SW node, or
let each buck have its own inductor to a common Cfilt on VOUT.
We designed in a current sharing scheme for the "live" ones
and the "sleepers" could just sit there and draw only IDDsb,
but could be brought online at any time if (say) one of the
others "lost its mind" - then disable it, and enable the spare.

Maybe some of those keywords will bear fruit in your search.

Suggest to look at the expectable waveform at the LC output filter when you short the lowside transistor. I'm rather sure you'll understand why you don't want this. There's a good chance to kill connected ICs with a high current negative supply voltage transient.

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