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@yuhiub90 Yes, I'm specifically stressing the fact that the Master A is of very low clock frequency, how long should the master B wait in that case.How is the Master designed for this?
I understand that but you have not answered my question, how does the arbitration work? Master has to be sure that SDA and SCL are high and whichever gets pulls the line low gets control,my question is specifically when the one master(very low speed) has control and SDA,SCL voltages are high...
Hi,
Consider this condition with multiple I2C masters assuming that there are speed restrictions, there are two masters A and B on a bus. Lets say the Master A's clock is very low speed and seeing SDA ,SCL lines as high and say later when Master A drive's logic both SCK and SCL high ,how does...
Hi,
I have a battery that can supply 5V @ 1 mA and has to source a circuit or board that needs 5V @ 2 mA. So I have a black box between them to achieve this functionality.So can anyone suggest me a circuit for the black box or an IC that meets this requirement.
Thanks
When SPI module/Ip is put to sleep , what should be the status of SCK ?Should it remain High(Ideal 0,0 mode).
If SCK goes low when put to sleep, wont there be an SCK edge when it wakes up/goes to sleep and SCK transitions?
Can u explain what you mean by error in your statement?
When i say errors i meant the wrongly settled states,Is it possible to reduce the probability of settling in the wrong states ?
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If your sampling rate is much higher then your asynchronous input signal. You can treat...
With the help of synchronizers we can definitely avoid meta-stability as it increases the settling time.
1)Does it ensure functional correctness(settling to the correct state)?
2)Can we detect these errors ?
3)How can we ensure functional correctness with synchronizers.
Im getting :32:14:32:24|No matching overload for "<" error for the following code
Process (clk, RST)
BEGIN
IF RST = '0' THEN
acc <= (Others => '0') ;
ELSIF (Clk = '1' and Clk'event) THEN
If acc = max THEN
acc <= (others => '0') ;
ELSE
acc <= acc + '1' ...
I just wanted to know which one is more critical as there is no direct relation between them and Hold time is taken care in complex designs automatically.
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