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Multiple I2C master problem

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bsbs

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Hi,

Consider this condition with multiple I2C masters assuming that there are speed restrictions, there are two masters A and B on a bus. Lets say the Master A's clock is very low speed and seeing SDA ,SCL lines as high and say later when Master A drive's logic both SCK and SCL high ,how does the MAster B know the bus is not free at this point.Note that both Master's are independent.
 

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master's (also slaves) can't drive either SCL or SDA high. They only drive the signals low and the protocol requires that the SDA be driven low to start a transfer. This is part of the arbitration scheme. The bus uses pullups for a high.

It's not terribly complex protocol and the specification is short. You can get more info here if you like.
 

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master's (also slaves) can't drive either SCL or SDA high. They only drive the signals low and the protocol requires that the SDA be driven low to start a transfer. This is part of the arbitration scheme. The bus uses pullups for a high.

It's not terribly complex protocol and the specification is short. You can get more info here if you like.

I understand that but you have not answered my question, how does the arbitration work? Master has to be sure that SDA and SCL are high and whichever gets pulls the line low gets control,my question is specifically when the one master(very low speed) has control and SDA,SCL voltages are high, how does other master know bus has already been taken .This is not clear in the spec
 

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@bsbs
Each master has start/stop detector. Timing interval between START and STOP signal is considered BUSY. Master B must detect these events. In case of 2 masters both see the bus is FREE and issue the START signal at the same time, bus arbitration will happen.
 

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@bsbs
Each master has start/stop detector. Timing interval between START and STOP signal is considered BUSY. Master B must detect these events. In case of 2 masters both see the bus is FREE and issue the START signal at the same time, bus arbitration will happen.

@yuhiub90 Yes, I'm specifically stressing the fact that the Master A is of very low clock frequency, how long should the master B wait in that case.How is the Master designed for this?
 

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I dont see problem of high/low clock frequency here. Master B must wait till it detects STOP event on bus to start its data transfer.
 
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The first master that releases sda (high) loses arbitration.
 

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