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Have a look at these papers:
Abidi group:
Behbahani et al, "CMOS Mixers and Polyphase Filters for Large Image Rejection", JSSC, June 2001
Allstot's group:
Fang et al, "An Image-Rejection Down-Converter for Low-IF Receivers", IEEE Trans. on Microwave Theory and Techniques, Feb 2005
I think he meant teh followng paper:
Remco C. H. van de Beek at al, "A 2.5–10-GHz Clock Multiplier Unit With 0.22-ps RMS Jitter in Standard 0.18-um CMOS"
Although normally people cite the authors last name, not the first! :)
I am looking for a 3rd edition of "PLL Performance, Simulation and Design" by Dean Banerjee. I've downloaded a copy from National's website, but it is print and copy text locked :(
If anyone knows where it's possible to get a pdf without these limitations, please share..
The modulator can be either descrete-time (switched-cap) or continuous-time (e.g gm-C) or even both (some stages descrete, some continuous).
The decimation filter is a digital circuit, that means FFs and logic.
delta sigma adc schematic
There's nothing mysterious in sizing & block design - this is basic analog design, if you can't do that, you'd first read books and practice building basic analog blocks (OTA, comparators) and then return back to SDM design :)
Regarding the books I've found useful...
opamp gbw 1t
hi lilac,
many OTA architectures are suitable for your design. You have not mentioned several things about your OTA:
- power supply voltage & target technology (Vt of transistor)
- required output swing
- power dissipation requirement
Your question makes no sense as it is too general..
The issues are:
1. length and width depend on your design, i.e. how long connection you need and how much wire resistance and capacitance your design can live with. There are also some design rules (provided by factory) limiting min wire...
Post simulation on ADC
I think that it is almost impossible to include the extracted parasitics to your simulation of the whole ADC in Spectre because of long simulation time. What can be done is including parasitics in the simulation of ADC blocks, then using this information in the behavioral...
Everything should be ok with your model :)
In periodic noise (PNoise) it is possible to have an option 'None' for input noise source if you do not need input-reffered noise or NF. I do not know why there's not such option in Noise analyses. But you can do as field_catcher has written - select...
There's smth wrong with your design. First of all, are you talking about signal harmonicsm or idle tones?
If you do not have harmonics at the output of the sigma-delta modulator (without any LP filter at all), you should not get harmonics after using comb filter if your filter designed...
for ADC:
DR is the ratio of input signal for which max SNR is achieved to input signal for which SNR=1.
You can read e.g. in Razavi's RF Microelectronics about it.
analog simulator poll
The results of pretty similar poll are here:
Another thing is that the poll has only one option - e.g. we are using both Cadence and ADS for different things.
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