issues related to wire(bus)

[mrigsharma]

respected all!!!!!
Can u people please let me know the length,width and the breadth of the wire (bus) used in any technology (50nm ,30nm or 90nm) technology doesnot matter.
This length has to be used by me to fix up the resistance and capicatence values for the interconnect

please help!!!!!!!

 

[j2005]

1. Find out the ohm/ sq for the metal
2. Find out if the resistance you get for the length, breath or whatever, is what you can tolerate in your design
3. Find out if the IR drop is OK for the design.

 

[mrigsharma]

The crux is that i want to know the values used in real practical usage by the designers.I checked out itrs but they had only mentioned the rc delay for some lengths.

 

[j2005]

The crux is that i want to know the values used in real practical usage by the designers.I checked out itrs but they had only mentioned the rc delay for some lengths.

In most cases, it really boils down to your design. But there's nothing to stop you from using minimum widths allowed by DRC rules for some non-critical nets.

 

[borodenkov]

Your question makes no sense as it is too general..
The issues are:

1. length and width depend on your design, i.e. how long connection you need and how much wire resistance and capacitance your design can live with. There are also some design rules (provided by factory) limiting min wire width

2. you can learn the Ohm/sq resistance (and possible MonteCarlo variations) from PDK docs and calculate the resistance of your wire.

 

[Teddy]

a) length depends on chip size etc.
b) for VEE/VCC bus you should be able to push enoug current through the bus to supply the chip. (I use 1mA/1um as a first estimate)
c) for analog design if you do some more stages which consume more surrent again you have to make sure that the wires are able to withstand it. If you put 0.5um wire for 1mA DC current it is sure what will happen
d) If you do real design you also have to make sure that the VCC/VEE bus is wide enough not to have too much of resistance/Vdrop in order to be sure that ESD structures will work
e) often you can find max length of the wire not connected to diffusion in antenna rules
f) width/length is limited by DRC (stress relief )
g) with some technologies you have to be very aware of the electromigration of the wires (this usually applies to vias/contacts) what often can dictate how you would do layout (ie IBM 5HP)

 

[mrigsharma]

thanks all!!!!!!!!!

 

[konqueror]

can any one tell what is the width of the supply lines used in different technologies and how are these values decided?

 

[crazyamd]

respected all!!!!!
Can u people please let me know the length,width and the breadth of the wire (bus) used in any technology (50nm ,30nm or 90nm) technology doesnot matter.
This length has to be used by me to fix up the resistance and capicatence values for the interconnect

please help!!!!!!!

check the design maunal or run a simple postlayout simulation