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Recent content by auroral

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    [MODELSIM] How to add signals to wave which is a child of the module being tested?

    Hello: So I have a separate modules foo (with signals: foo_a, foo_b, foo_c) and have another module foo1 (with signals: foo_x, foo_y, foo_z) which instantiates foo within its module. Now when I run a test on foo1, on ModelSim, the signals I can see to add are the foo_x, foo_y and foo_z only...
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    Verilog wrapper module help

    Hi, I'm a beginner and am trying to find out how to go about this module. This module has a bunch of SRAMs (single port) All it does is read incoming data one-by-one and <once a particular condition is satisfied> outputs out all the data at once. How do I code this module for [this...
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    Instantiation inside an if loop?

    Can I instantiate modules inside an if loop? Basically I want to instantiate some modules only if some condition holds true. If I can't do it, what is the workaround? Thanks.
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    Using a single port SRAM

    Hi, I have a bunch of signals(X1,X2,X3,Y1,Y2,Y3) coming out of a module A, and these need to be stored in a single port RAM and immediately sent to another module B. My question is how do I instantiate my RAM (how do i use the 'en' signal at once for both read and write). RAM r1...
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    compile command disabled on ICC

    Hello, When I tried to run compile or compile_ultra, IC Compiler tells me that they are disabled? cc_shell> compile_ultra -incremental -scan Error: Command 'compile_ultra' is disabled. (CMD-080) icc_shell> compile Error: Command 'compile' is disabled. (CMD-080) Is there a way to turn it ON...
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    Milkyway: Reference Library Inconsistent With Main Library

    So, when I created a milkyway library with a reference library, it says that the Reference Library is Inconsistent With Main Library. Warning: Inconsistent Data for Layer 43 Main Library (mw) | Reference Library (CORE90GPLVT) Layer Name CB2 | CB Mask Name (null...
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    setting up milkyway lib for ic compiler

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    Formality warnings - Cannot link cell

    Where (path) do I find the right db file? In my design lib or software techfile lib? Thanks!
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    setting up milkyway lib for ic compiler

    When I open and get into the milkyway dir and try to import my verilog design, this is what happens. icc_shell> open_mw_lib example/ {example} icc_shell> import_designs -format verilog -top icc_test -cel icc_test {/xyz/example/rtl/icc_test.v} Loading db file...
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    setting up milkyway lib for ic compiler

    Hi, I'm pretty sure I'm going wrong on setting up the milkyway library for running ICC. Help me fix it! I create a milkyway lib using create_mw_lib -technology <filename> <libname> and then open_mw_lib <libname> and then go on to import my verilog design files. The designs run clean on DC...
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    IC compiler for system verilog?

    Thanks again! I couldn't sign in to Solvenet. My license SiteID shows 000. So couldn't signup. Anyways, I just tried a read_sverilog (like in Formality) and it apparently works.
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    Formality warnings - Cannot link cell

    I was planning to run Formality to verify my SV design. In Stage 1 (Reference) I feed the file, and it accepts without an error. Now when I try to set the top module, I run into several warnings and at the end Formality stops and fails to set the top module. I get warnings like these: ... ...
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    IC compiler for system verilog?

    Thanks, paulki. I was trying to run an SV design, and ICC was complaining on the always_comb and other SV constructs. So, how do I go about fixing this with Synopsys?! Thanks.
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    IC compiler for system verilog?

    Is the IC Compiler known to be used to import System Verilog designs?
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