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Hi Aurorel,
IC Compiler is supporting SV designs, you'll get any supoports from Synopsys on that.
But the reply from ljxpx is misleading, "irun" command will work for the Cadence Simulation tools, not for the Synopsys Compiler tools!!!
Thanks, paulki. I was trying to run an SV design, and ICC was complaining on the always_comb and other SV constructs. So, how do I go about fixing this with Synopsys?! Thanks.
Check in the Synopsys Solvenet site any additional switches (+sv) are required to pass while doing ICC for the SV designs. This will help you to resolve the issue.
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