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Recent content by ashishk

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    multiple uvm sequence to run on same sequence in parallel

    I have 2 sequences in UVM which need to run on same sequencer in parallel. e.g. seq1 generates 10 pkt viz pkt1-pkt10 with some random delays in between. seq2 also generates 10 packets of same type pkt11-pkt20. I fork these both seq1 and seq2 and what i see that packets are either generated in...
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    [SOLVED] Error in SV module compilation

    Hi Dave, Second solution seems to have syntax error and I am getting error for that. As I told you that my top TB is in VHDL so I don't think taking an instance of interface at top will work. That's why I was taking intance of interface inside mdio_phy module and from there I was doind port map...
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    How to dump multi dimensional arrays in vcs

    no solution found for this :( So as of nowI am running simulation in gui mode and adding those in waveform window before giving run command.
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    [SOLVED] Error in SV module compilation

    Hi, My TB is in VHD and I created a bfm(mdio_phy) in verilog as follows: ************************************* interface mdio_if; logic clk; logic nRst; logic mdio; endinterface:mdio_if module mdio_phy ( inout mdio, input mdclk, input nReset ); **************** code...
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    Unassociated port error during elaboration of design

    Hi, I am using vcs for simulations.RTL is in VHDL. During elaboration phase I am getting one error "Error-[ANL-UNASSO-PORT] Illegal port association , Unassociated port <port_name> of mode IN in entity <entity_name> has no default value. Can anyone tell me what does this mean? Thanks, Ashish
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    How to dump multi dimensional arrays in vcs

    waiting for some quick replies....
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    How to dump multi dimensional arrays in vcs

    Hi, I my design i am having a MDA reg . I am dumping whole design during my simulation( non gui mode) and after simulation i load .vpd in dve waveform viewer but it doesn't show me MDA dumped. It says None of the children of the object MDA is dumped. Can anyone help me in solving the issue...
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    purpose of analog mix signal simulations?

    But why do we have it at first place. Cant we verify digital block and analog block separately. Is the purpose of this is to check connectivity? I dont believe this.There got to be something else that we are achieving but I don't know that. Can you please explain. Thanks, Ashish
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    purpose of analog mix signal simulations?

    Hi, Can anyone please tell me what is real purpose of doing analog mix signal simulation with digital and analog netlists? When we already do digital functional verification with analog behavioral models and spice simulations for analog separately then why do we need to do AMS. Is it something...
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    query regarding gate level simulations??

    Hey thanks but I wanted to know if during simulations I get error messages for setup/hold violations then is that because of issue in flops or it may be fake? I understand issue arising due to not initializing flops
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    query regarding gate level simulations??

    Hi, I have a query regarding GLS. What would be the fake issues getting reported during gate level simulations? As I understand that whatever violations come during GLS should be fixed. Am I correct? What else could come? ~Ashish
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    How c based verification is done for ARM based SOC

    Also If someone can help me in understanding the ARM RVDS flow. I tried reading from ARM website but didn't understand much.
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    help me with verilog code

    One clarification. I want to know if in sensitivity list we can do '&' and '|' operation? And when it will get triggered.
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    help me with verilog code

    Hi, I am a verification guy and want to know if following verilog codes are valid or not: 1) always @( a & b) 2) always @(a || b) 3) always @(a && b) 4) always @(a | b) Thanks
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    ASIC Verification position tips and tools?

    Apart from Verilog,try to learn some HVL as well like system verilog. Now a days most of the people use SV for verification.Since you already know C++ so you should not be having any issues with OOPs concepts of SV . For learning it you should be readinf from LRM(IEEE 1800-2009) or can refer...
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