Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

query regarding gate level simulations??

Status
Not open for further replies.

ashishk

Junior Member level 2
Joined
Dec 29, 2010
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,419
Hi,

I have a query regarding GLS. What would be the fake issues getting reported during gate level simulations? As I understand that whatever violations come during GLS should be fixed. Am I correct? What else could come?

~Ashish
 

Hey thanks but I wanted to know if during simulations I get error messages for setup/hold violations then is that because of issue in flops or it may be fake? I understand issue arising due to not initializing flops
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top