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Recent content by arbalez

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    About Microchip Explorer 16 Development Board

    explorer16 hi, i want to ask this newbie question to those who are familiar with this Explorer 16 board. what i want to know is how i can connect the TX, RX and I/O to MAX485/MAX483 since there's no input/output port on the board. there's only one prototype area. this development board is...
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    Question about rising_edge and falling_edge function

    rising_edge non clock signal can rising_edge() and falling_edge() be used to detect non-clock (asynchronous) signal? is it only meant for clock signals?
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    Quartus II warning messages: need advices

    After doing full compilation of my design, i got the following warning messages. the documentation does not explain in detail on how to solve the problem. i do hope that somebody who had experienced this before could advice me. Critical : Design Assistant Warning: Logic cell should not be used...
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    help in "K counter" of ADPLL (VHDL source code)

    Re: help in "K counter" of ADPLL (VHDL source code yeah, just set the K width (UP and DOWN) width to be the worst-case one (or the largest available width you preferred). then by getting the 4-bit input for k-counter configuration, you can use the available width according to your need. for...
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    help in post&map simulation

    how you solved it?
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    help in "K counter" of ADPLL (VHDL source code)

    Re: help in "K counter" of ADPLL (VHDL source code i do not really understand what bound you are trying to define. but you can try this (k-counter values are according to CD74ACT297 datasheet): if K = "0001" then k_val := 8; elsif K = "0010" then k_val := 16; elsif K = "0011" then k_val...
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    help in "K counter" of ADPLL (VHDL source code)

    actually i'm doing the same project. i did the k-counter but now still solving the i/d-counter part. Added after 2 minutes: there is no code of ADPLL released to the public, as far as i know.
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    Should the use of variables be avoided for synthesis?

    Re: variables and synthesis finally, i realized my mistake after doing some reading. i just knew that variables and signals cannot be initialized for synthesis. i must use reset mechanism to initialize variables or signals as the code below, if (reset = '1') then variablename := 0; else...
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    Should the use of variables be avoided for synthesis?

    Re: variables and synthesis yup. i'm using vhdl. the fact is i can synthesize my code. but got many warning messages related to the variables. most of the variable registers are stucked to GND or VCC. whenever i assigned any variables := 0, then it will stuck to GND. i've checked my synthesis'...
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    synthesis: is my code fully RTL?

    do you mean here that the code of the pre-synthesis (functional/behavioral) is usually not the final code? and the post-synthesis modification of RTL code is usually the final code of a design (that is guaranteed to work even if we do functional/behavioral simulation),
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    functional simulation does not work

    first i used quartus-based simulation it failed. then i used modelsim, also failed.
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    synthesis: is my code fully RTL?

    i understood now. so successful synthesis doesn't mean that it will function as it supposed to be right? in the end, i need to change the code. that's sure a lot of work :) i wish myself can think in hardware. thanks all.
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    synthesis: is my code fully RTL?

    if i can synthesized my design code without any error. does it mean that i had written 100% RTL code? in other words, is the code that can be synthesized can be considered 100% RTL? i'm asking this because my gate-level simulation failed to show any positive result.
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    post-synthesis modelsim error

    zero-delay oscillation loop modelsim thanks for replying. this is my test bench. it's generated by QuartusII. i also have set higher "iterationlimit" (instead the default of 5000) in modelsim but i still got the same error. i'm not putting anything in the sensitivity list, so there shouldn't...
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    Should the use of variables be avoided for synthesis?

    how initialize variable in synthesizable verilog is it true that we have to avoid the use of variables if we want our code able to be RTLed? thus able to be synthesized?
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