help in "K counter" of ADPLL (VHDL source code)

[yming]

adpll vhdl

anyone help me in how to write the vhdl code of k counter, the programmable part? the variable stage long which controlled by the K modulus.
or giv me some direction because i cant find any sources in internat.
thank you.

 

[yming]

Re: help in "K counter" of ADPLL (VHDL source code

no one know that? then....

does anyone know whether the bound can make variable?
for eg.
UP : std_logic_vector(N downto 0);
the N is not constant but will depend on the other input port. or hav any method to solve it?
thanks first.

 

[vomit]

Re: help in "K counter" of ADPLL (VHDL source code

A counter modulus K (programmable) needs a fixed worst-case port width for K.

Then it is just a decrementing counter with synchronous preload like

process(Clk)
begin
  if rising_edge(Clk) then
    if Count=0 then
      Count<=K;
    else
      Count<=Count-1;
    end if;
  end if;
end process;

 

[yming]

Re: help in "K counter" of ADPLL (VHDL source code

thank you vomit.

but i not really understand what u mean?
what is the propose of that Count? and what data type of Count, same as K (std_logic_vector(3 downto 0)?

 

[arbalez]

actually i'm doing the same project. i did the k-counter but now still solving the i/d-counter part.

Added after 2 minutes:

there is no code of ADPLL released to the public, as far as i know.

 

[yming]

anyway, arbalez, i know there is no code to released, but can u giv me a little guide?
thanks

 

[arbalez]

Re: help in "K counter" of ADPLL (VHDL source code

no one know that? then....

does anyone know whether the bound can make variable?
for eg.
UP : std_logic_vector(N downto 0);
the N is not constant but will depend on the other input port. or hav any method to solve it?
thanks first.

i do not really understand what bound you are trying to define. but you can try this (k-counter values are according to CD74ACT297 datasheet):

if K = "0001" then
 k_val := 8;
elsif K = "0010" then
 k_val := 16;
elsif K = "0011" then
 k_val := 32;
end if;

and so on...
note: assume k_val is declared earlier as variable.

make sure the k_val variable is shared among all processes in your k-counter architecture.

architecture rtl of k_counter is
shared variable k_val : integer;
...
end architecture k_counter;

it's a bit hard to defined the bound through entity declaration although you can do it, but it will cause extra work later in the architecture if you want to synthesize your code. for me, so i just define the bound during declaration in the first place (made it 4-bit).

 

[arbalez]

Re: help in "K counter" of ADPLL (VHDL source code

A counter modulus K (programmable) needs a fixed worst-case port width for K.

Then it is just a decrementing counter with synchronous preload like

process(Clk)
begin
  if rising_edge(Clk) then
    if Count=0 then
      Count<=K;
    else
      Count<=Count-1;
    end if;
  end if;
end process;

yeah, just set the K width (UP and DOWN) width to be the worst-case one (or the largest available width you preferred). then by getting the 4-bit input for k-counter configuration, you can use the available width according to your need.

for example, as you set the k-counter width to be 32-bit wide (it is fixed), it is the worst-case/largest one. so you can't configure the k-counter or set K for value more than 32. but you can still set for K value that is below than 32. so no problem if you want to use K value of 8 or 16, although there will be extra bits left.

the code you had written, i think is just possible to be used in simulation only, maybe by setting N as the global variable, or generic value in the top-level design. but not for synthesis because we are defining hardware. and hardware needs precise ports definition.

UP : std_logic_vector(N downto 0);

hope that helps.