Question about rising_edge and falling_edge function

[arbalez]

rising_edge non clock signal

can rising_edge() and falling_edge() be used to detect non-clock (asynchronous) signal? is it only meant for clock signals?

 

[parvati]

rising_edge + asynchronous

no, basically the clock signals are used for the synchonization between two signals,modules. if you produce a equal delay in between the signals that the signal will reach the output at the same time then you will not need the clock that is also known as clock less logic.

 

[maksya]

rising_edge falling_edge

Examine description of these functions in IEEE.std_logic_1164 library. And it will be clear for you, that there is no opportunity to use them is asynchronous design. synthesizer interpret the argument of these functions like clock signal.

 

[sp]

rising_edge of two signals

i think it can b use to detect any rising edge of a signal...

i try it wth my motor spplication n it works (non-clk)... as in the ieee.std_logic_1164 lib.. it is just

(s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE) = '0'))

so any rising edge of a signal will trigger it...

anyway, tht's wad i hav done using altera quartus2..

regards,
sp

 

[radix]

As Sp stated, you can capture the rising edge of a signal that is asynchronous to the main system clock using a flop that is clocked by the asynchronous signal. However, you will still need to use traditional synchronization techniques to synchronize the two different clock domains.

Radix