Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
no, basically the clock signals are used for the synchonization between two signals,modules. if you produce a equal delay in between the signals that the signal will reach the output at the same time then you will not need the clock that is also known as clock less logic.
Examine description of these functions in IEEE.std_logic_1164 library. And it will be clear for you, that there is no opportunity to use them is asynchronous design. synthesizer interpret the argument of these functions like clock signal.
As Sp stated, you can capture the rising edge of a signal that is asynchronous to the main system clock using a flop that is clocked by the asynchronous signal. However, you will still need to use traditional synchronization techniques to synchronize the two different clock domains.