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Recent content by Anil Rana

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    include file in verilog

    In `include <filename path> keep <filename path> relative to directory where you are compiling.
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    help system verilog questions

    does nc verilog support system verilog Hi All I need some information about system verilog. Please help me in this regard 1) Is system verilog used widely? 2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog? 3)which tools support...
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    help needed on clock generation

    Thanks echo47 I think i have to consider both the methods before implementing
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    help needed on clock generation

    echo47 wrote yes echo47 .This is used as a requirement for testbench.
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    help needed on clock generation

    Hi all Can anyone suggets how to generate a clock which will give don't care 'X' on specific time.I know how to generate it but Please suggest a compact way Thanks in advance
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    Perl applications in EDA

    blif nor good job jimjim2k keep it up
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    help in code coverage in ncsim

    i would like to clear myself .actually i needed methods to perform code coverage in nc verliog which the topic **broken link removed** do not explain will anybody help me?[/url]
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    help in code coverage in ncsim

    hi all how to perform code coverage in ncsim?like cmds ,methods etc... thx
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    help delta delays in verilog code

    thanks a lot
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    help delta delays in verilog code

    delta delay in verilog hi all can anyone suggets me how to calculate the number of delta delay in verilog code?As in vhdl it is clearly defined and quite easy to infer the exact number of delta delays required for new transaction.I have written a code for testbench which reads from a file...
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    help needed in vhdl simulation in ncvlog

    vhdl ncverilog waveform yes lucano i am using vhdl in ncverilog. and use ncvhdl -cmds to compile and simulate ,to view waveforms i need help ,since it can be done using ncsim -gui options,and we don't have that feature supported or let's say don't have licence. That 's why i needed help in...
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    help needed in vhdl simulation in ncvlog

    compiling vhdl with ncverilog Actually when i tried for waveform viewing using ncsim -gui cmd ,the simulator prompted to use ncsim -message cmd since some licencse problem was there. and hence the question to invoke simvision using ncsim -message cmd.hope you people got this regards
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    help needed in vhdl simulation in ncvlog

    use ncvlog to compile vhdl files thanks ammoccormack but the problem is after compiling.elaborating and simulating if i open the waveform winndow by giving the simvision cmd i can't see any w/fs.It may be due to i don't have any "dump" file like in verilog. My question is there is any othe...
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    help needed in vhdl simulation in ncvlog

    ncverilog vhdl hi all what are the commands/steps needed in simulation and waveform viewing for ncvlog while the code is in vhdl.We don't have the gui capability in our cadence enviroment. thanks
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    Why PAD in ASIC layout is given special importance ?

    PAD query? hi all Why pad in ASIC layout is given special importance ? can any body elaborate. Tahnks all
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