help needed on clock generation

[Anil Rana]

Hi all
Can anyone suggets how to generate a clock which will give don't care 'X' on specific time.I know how to generate it but Please suggest a compact way
Thanks in advance

 

[echo47]

Are you referring to a simulated clock, such as a Verilog or VHDL test bench?

 

[Anil Rana]

echo47 wrote

Are you referring to a simulated clock, such as a Verilog or VHDL test bench?

yes echo47 .This is used as a requirement for testbench.

 

[echo47]

I can't think of anything very compact.
Here's a Verilog module that outputs a clock of period 10 that becomes 'x from time 23 to 39:

module top (clk);
  reg     toggle=0, gate=0;
  output  clk;

  always  #5 toggle = ~toggle;
  initial #23 gate = 1;
  initial #39 gate = 0;

  assign clk = gate ? 'x : toggle;
endmodule

Anyone know a more compact method?

 

[jjww110]

you can use force command in simulation tool such as modelsim

 

[Anil Rana]

Thanks echo47
I think i have to consider both the methods before implementing