help delta delays in verilog code

[Anil Rana]

delta delay in verilog

hi all
can anyone suggets me how to calculate the number of delta delay in verilog code?As in vhdl it is clearly defined and quite easy to infer the exact number of delta delays required for new transaction.I have written a code for testbench which reads from a file the and applies that to the input of dut which also depend upon the valid signal again an input to the dut.what care should be taken for in this case?

regards

 

[AlexWan]

Hi, Anil Rana

You can find a paper named "Correct Methods For Adding Delays To Verilog Behavioral Models" in the Cumming's site.

h**p://www.sunburst-design.com/papers/

 

[Anil Rana]

thanks a lot