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help system verilog questions

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Anil Rana

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does nc verilog support system verilog

Hi All
I need some information about system verilog. Please help me in this regard

1) Is system verilog used widely?
2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?
3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?
4)Is it features both synthesizable and simulation specific constructs?
5)How can learn system verilog ?
6)How does it fit with VHDL,system C,Vera and Specman?
 

wadaye

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Hi Anil Rana,

Here is some answers.

1). Systerm Verilog not use widly.

3). Some tool support systerm verilog, pls check the user guide/release info to confirm.

Added after 2 minutes:

Hi Anil Rana,

Here is some answers.

1). Systerm Verilog not use widly.

3). Some tool support systerm verilog, pls check the user guide/release info to confirm.
 

zhan

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(1) NC-verilog support system verilog in ISU56
(2) System Verilog fit for system specification, it's subset can be used to synthesis
 

aji_vlsi

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Anil,
Some answers:

Anil Rana said:
1) Is system verilog used widely?

Adoption is increasing, since SV is a large language, it will be hard to measure this. AFAIK, lot of people started using/showing interest in SV. Read deepchip.com, verificationguild.com etc. for more staistics.

2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?

Yes, it is 100% backward compatible. Infact SV LRM is over and above V2K LRM.


3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?

I know VCS does it a lot. Mentor's Questa, NC etc. also support. From what I read on web, NC seems to be little behind. I believe you need a switch such as -sv31a or some thing like that - read their manual.


4)Is it features both synthesizable and simulation specific constructs?

Some design specific extensions (such as interface/struct, always_comb etc.) are synthesisable, DC already supports them.

5)How can learn system verilog ?

By trying it out - lot of material is available on net and tool-vendors' doc. For e.g. see: www.project-veripage.com

6)How does it fit with VHDL,system C,Vera and Specman?
[/quote]

A good tool - platform (such as VCS, Incisive, Questa) support all of these in one environment.

HTH
Ajeetha
www.noveldv.com
 

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