Anil Rana
Junior Member level 1
does nc verilog support system verilog
Hi All
I need some information about system verilog. Please help me in this regard
1) Is system verilog used widely?
2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?
3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?
4)Is it features both synthesizable and simulation specific constructs?
5)How can learn system verilog ?
6)How does it fit with VHDL,system C,Vera and Specman?
Hi All
I need some information about system verilog. Please help me in this regard
1) Is system verilog used widely?
2)can I use system verilog in verilog 2001 environment,i.e. is it backward compitable with verilog?
3)which tools support system verilog?Do NC-verilog support it?Are there any special command other than common ones in a tool to simulate system verilog?
4)Is it features both synthesizable and simulation specific constructs?
5)How can learn system verilog ?
6)How does it fit with VHDL,system C,Vera and Specman?