include file in verilog

[senddilu]

verilog include file

For including a file in verlog, i used `include in a test module. So my aim
was to call the tasks that are defined in the file 'include "task_def.v"
while compliling, i have tried compiling both the test module and task_dev.v
Modelsim is reporting lots of errors for the variables declared in the files.
How to get rid of the problem.?
-Thanks
Senddilu

 

[HolySaint]

verilog include

only compiling the file which includes the task file is ok

 

[ljxpjpjljx]

include files in verilog

also you should add some option!

 

[m2star]

how to include the file in verilog please help.............
i use `include <filename> but its not working.........

 

[ljxpjpjljx]

when you do simulation , you should also add it in include path!

 

[Anil Rana]

In `include <filename path> keep <filename path> relative to directory where you are compiling.

 

[maheshkumar.g]

i have the same problem too but how to include the filename path please explain with example so that we can understand....thanks

 

[sakthikumaran87]

Hei better keep all the files in the same folder and in coding where u use the defines, as a first line : `include xyz.v then when simulating it is better to : vlog src/*.v; vsim src/*.v
this is done so that the included file is also compiled along with the design files