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Recent content by am85

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    Lattice ICE40 programming

    Hi everyone, I am using a Lattice FPGA for the first time and It is really different than Altera and Xilinx. I am having several problems so hopefully anyone can help. I am on Windows 8, I have Ice cube 2 and the ICE40blink HX1K evaluation board. First of all there is no programmer in the...
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    Clock Domain Crossing betweem RMII to MII Converter and FPGA Transceiver

    The Transfers are in both directions. OK so would a handshake based on the Clock enable from TSE be enough or I have to use a FIFO?
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    Clock Domain Crossing betweem RMII to MII Converter and FPGA Transceiver

    Yes. However, the MII data from TSE are stable for 40 ns (25 MHz clock enable) and doesn't change every clock cycle with the 125 MHz clock, so with the converter's 50 MHz clock I will never miss any data. Do I still need CDC techniques between Converter and TSE ?
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    Clock Domain Crossing betweem RMII to MII Converter and FPGA Transceiver

    Hi, We are connecting a 100Mbit Ethernet PHY to an FPGA via RMII. We wanted to connect it the RMII interface to the FPGA transceiver (Altera TSE with PCS + PMA only) to send the data via SGMII to another device, so we have an RMII to MII converter since TSE has no RMII interface. The Converter...
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    Clock Domain Crossing between RMII to MII Converter and FPGA Transceiver

    Hi, We are connecting a 100Mbit Ethernet PHY to an FPGA via RMII. We wanted to connect it the RMII interface to the FPGA transceiver (Altera TSE with PCS + PMA only) to send the data via SGMII to another device, so we have an RMII to MII converter since TSE has no RMII interface. The Converter...
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    1000Base-T propagation delay

    yes the calculation of the PCB trace delay is easy, and anyway it's just picoseconds so it is insignificant compared to the PHY delay in nanoseconds. Our problem is to include the PHY delay in the propagation delay measurement or calculation.
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    1000Base-T propagation delay

    The interface between FPGA and external PHY is SGMII. We want to measure the delay to be able to compensate for the asymmetry of RX and TX to improve the IEEE1588 synchronization.
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    1000Base-T propagation delay

    Hi, We have an FPGA connected to an external 1000Base-T Ethernet PHY. We are trying to measure the propagation delay of only one way TX or RX from FPGA to the Ethernet connector or vice versa. We can only measure both ways together but this won't help as they are asymmetric. We tried to measure...
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    SD card long random write delays in SPI mode

    I am trying now to perform a pre-erase CMD before writing. I am trying ACMD23 and also CMD32,33 and 38. It is not working yet. I am also trying CMD6 for high speed mode but also not working.Does it work with SPI mode? I would appreciate any help on how to issue these commands and the sequence...
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    SD card long random write delays in SPI mode

    Thanks for your reply. Firstly, I format the SD card using windows format option, then copy and paste a 2 GB empty file to the card. Then , I write continuously(not single blocks) directly to the sectors starting by the address where the file begins. From what I read, this command is done...
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    SD card long random write delays in SPI mode

    Hi, I am using a 32 GB 400x SDHC card. I am writing to the SD card using SPI mode at 50 MHz. I use a Buffer to store the data first and then write to the card. 512 Bytes from the buffer are ready for the SD card every 100 us. Normally, it takes around 88 us to write one sector on the SD card...
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    Voltage divider for a square wave

    Yes I have read about this compensation capacitors. One source suggested having capacitors in parallel to every resistor of the voltage divider, but it didn't work. So can u please explain a bit more where exactly i should connect these capacitors. I have the voltage divider built in the cable...
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    Voltage divider for a square wave

    Hi, I am reading a high voltage square wave using an ADC. Firstly, I have a voltage divider using a 500k ohm resistor on every line coming from the wave generator and a 1.5k ohm resistor between both lines. Then comes the programmable amplifier and the ADC. I get the following plot : Is this...
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    Delay between state signal and output signal

    Yes it is causing me lots of problems. The fast clock domain(100MHz) is performing fast calculations on ADC data. Then it sends the results to the SPI module(slow clock domain 1MHz) to be sent to a µC. The faster module detects the rising edge of the flag (results are ready) and then sets...
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    Delay between state signal and output signal

    I solved the problem. The data_ready signal in the if condition is coming from a faster clock domain, so I put it first into a register before the if condition then it worked fine. But I am not sure why this was happening because this signal is just a flag set to high til the slow clock domain...
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