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Clock Domain Crossing betweem RMII to MII Converter and FPGA Transceiver

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am85

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Hi,

We are connecting a 100Mbit Ethernet PHY to an FPGA via RMII. We wanted to connect it the RMII interface to the FPGA transceiver (Altera TSE with PCS + PMA only) to send the data via SGMII to another device, so we have an RMII to MII converter since TSE has no RMII interface. The Converter uses the same 50 MHz clock as the PHY and converts between the 4-bit MII and 2-bit RMII. However, the FPGA transceiver has a clock of 125 MHz and a 25 MHz clock enable signal in MII mode.

Are clock domain crossing techniques required here? and which one would fit the best ?

Thanks.
 

From what I can interpret from your description there is a 50 MHz clock source running the PHY and the converter and another 125 MHz clock source running the TSE? If so then the clocks are asynchronous as they aren't frequency and phase locked, so you'll have to apply CDC techniques to the control and data. I would suggest a using a pair of shallow tx/rx async FIFOs, an extra logic to compensate for differences in clock frequencies between the 50 MHz and the 125 MHz (25 MHz clock enable).
 

Yes. However, the MII data from TSE are stable for 40 ns (25 MHz clock enable) and doesn't change every clock cycle with the 125 MHz clock, so with the converter's 50 MHz clock I will never miss any data. Do I still need CDC techniques between Converter and TSE ?
 

Yes. However, the MII data from TSE are stable for 40 ns (25 MHz clock enable) and doesn't change every clock cycle with the 125 MHz clock, so with the converter's 50 MHz clock I will never miss any data. Do I still need CDC techniques between Converter and TSE ?

You seem to be looking at transfers in only one direction?

The clocks are not synchronous, you've already answered your own question, which ever direction you are going 50->125(25) or 125(25)->50 you are going to be sampling the data transferred in that new clock domain, which aren't frequency and phased locked to each other. How do you expect to sample synchronously or when it's okay to sample if the clocks can drift.

So tell me how do you expect the transfer from 25M enable to 50 is going to work? What if the 25MHz is off by say +300 ppm and the 50 MHz is off by -300 ppm? So now the clock periods are actually 20.006 ns and 39.988 ns now the clocks edges are going to drift, how are you planning on compensating for this?


Treat them as truly asynchronous or not is your choice, you'll be the one working late nights in the lab trying to fix it when systems start failing in production test.
 

The Transfers are in both directions. OK so would a handshake based on the Clock enable from TSE be enough or I have to use a FIFO?
 

Don't you understand, if the clocks are not synchronous the edges will drift in relationship to each other. So no, a simple handshake will probably end up with intermittent unexplained failures.

A safe/conservative design would be use a FIFO with a circuit to insert/remove idle symbols to compensate for clock frequency differences, but it's up to you...maybe you like living in the lab/office (is there free food involved? ;-))
 

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