1000Base-T propagation delay

[am85]

Hi,
We have an FPGA connected to an external 1000Base-T Ethernet PHY. We are trying to measure the propagation delay of only one way TX or RX from FPGA to the Ethernet connector or vice versa. We can only measure both ways together but this won't help as they are asymmetric. We tried to measure an Ethernet frame using an Oscilloscope but we failed to detect the start of a frame (or difference between idle and real data) due to the 4D-PAM5 encoding. We can't also find any information about the delay of the PHY chip.
any ideas?
Thanks in advance.

 

[sankar.m8]

If you have a layout file, you can simulate using Hyperlynx for the propagation delay. What is the interface used between FPGA & Ethernet PHY ? RGMI/GMII ? Why do you want to measure the propagation delay ? As a general guideline, once you matched the Tx & Rx pairs with clock, delay can be implemented inside the PHY.

 

[am85]

The interface between FPGA and external PHY is SGMII. We want to measure the delay to be able to compensate for the asymmetry of RX and TX to improve the IEEE1588 synchronization.

 

[sankar.m8]

You can calculate the propagation delay theoretically. For a FR4 PCB Material (Er=4.3), 1 Inch of PCB trace on Inner layer will result a time delay of 176psec & in Outer layer, it will be around 146psec (For 1oz copper, 5 mils trace). Hyperlynx software also you can use to find out the propagation delay.

 

[am85]

yes the calculation of the PCB trace delay is easy, and anyway it's just picoseconds so it is insignificant compared to the PHY delay in nanoseconds. Our problem is to include the PHY delay in the propagation delay measurement or calculation.

 

[cherjier]

Hi am85,

Usually those information need to come from the manufacturer. they can estimate the delay for TX and RX base on simulation of their PHY design. Here is an example report that Vitesse release their PHY delay: https://www.google.com.my/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CCsQFjAA&url=https%3A%2F%2Fwww.vitesse.com%2Fproducts%2Fdownload.php%3Ffid%3D4307%26number%3DVSC8558&ei=qXxPU4h4gf6sB9fVgcAF&usg=AFQjCNE3O2ZDiwYbyf5mfmfMqBSqIW2x9w&sig2=aoO4sEuId14CKm2m8BZNmw&bvm=bv.64764171,d.bmk

However, FPGA usually provide hardware time stamp solution that perform timestamp function on the FPGA Pin level, in that case, the delay on the asynchronous TX and RX path can be compensate base on the PTP protocol. The only downside is the error of the accuracy could be larger due to indeterministic latency on the PHY path.