am85
Member level 2
Hi,
I have a design with several states implemented using case statements. In one of the states I assign 2 signals, the state signal and an output signal. After one clock cycle, the output signal(counter) is changed while the state signal requires one more clock cycle to change, so the same state is accessed again instead of the new state. What could be causing this delay?
A part of the code is as follows:
Thanks.
I have a design with several states implemented using case statements. In one of the states I assign 2 signals, the state signal and an output signal. After one clock cycle, the output signal(counter) is changed while the state signal requires one more clock cycle to change, so the same state is accessed again instead of the new state. What could be causing this delay?
A part of the code is as follows:
Code:
case state is
when setup =>
if data_ready = '1' then
state <= start;
counter <= "001";
end if;
when start =>
Thanks.
Last edited: