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always @ (posedge clk_153)
start_reading <= 1'b0 ;
if(condition1) // once this condition occur start_reading is always high
start_reading <= 1'b1 ;
always @ (posedge clk_102)
Dear EDA Board members,
let us take one example with Burst Length=8, Number of Bytes=4 and Starting address=0x4a and data needs to be transferred using Wrapping Burst.
I have calculated the address of each transfer with respect to equations given in AMBA AXI Protocol Version 2.0 Specification...
While designing a cache we should satisfy the condition
cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem.
there are very less information available regarding overcoming aliasing (anti aliasing...
Re: c library call from assembly generated by gcc from some c code
I have done single step gdb debugging,
#addsd %xmm1, %xmm0 # commented actual addition
call add # added my library call here
movsd %xmm0, (%rax) # segmentation fault here
The assembly of add.c is given below, where it is operating on %xmm0 and %xmm1, and in actual assembly this add call should actually work .
gcc -c add.c
ar -crv libtemp.a add.o
gcc -S exp1.s -ltemp L. exp1.o
gcc exp1.o -o exp1 -ltemp L.
./exp1 -- segmentation fault
I am experimenting on modifying assembly by calling c library from assembly, I ran into segmentation fault
double a_d = 1.1;
double b_d = 2.1;
c = &c_d;
a = &a_d;
b = &b_d;
*c = (*a + *b);
I have a third party software floating point library which was compiled using 64 bit machine (-m64). I am trying to infer this floating point library using gcc flag -msoft-float.
If I am using gcc -msoft-float -m32 flag for c = a+b, where c,a,b are float values,gcc infers...
with TIG, it simply ignores the timing for all those paths with cdc even if it is not meeting (considering all those paths which are failing), so I don't know whether that is an efficient way. I didn't get why you have written 3*4
Thank you dpaul and ads-ee for solutions. I used keep = TRUE attribute and pinned to the top level in the hierarchy.
and used $monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.my_iteration1 ); but I got
Unresolved reference to 'my_iteration1' in...
I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast...
While doing CDC, I am using 3 flop synchronizer from slow clock(100MHz) to fast clock(250MHz).
It is reporting timing not met as (I am using xilinx 14.7 for synthesis)
Source Clock: clk_100 rising at 10.000ns
Destination Clock: user_clk rising at 12.000ns
but actually it should report...