Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Anti aliasing in VIPT cache

Status
Not open for further replies.

achaleus

Member level 5
Joined
Dec 21, 2012
Messages
85
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Location
Bangalore
Activity points
1,866
Dear edaboard,
While designing a cache we should satisfy the condition

cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem.

there are very less information available regarding overcoming aliasing (anti aliasing hardware), any papers eliminating this issues are most welcome.
many cache designs generally have 16kb 2 way I-cache and 32KB 4-way D-cache designs, but how they are eliminating aliasing (considering not every OS do page coloring and supports only 4KB pages) in cache design.

Thank you,
Vinay
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top