CDC for constant signal

[achaleus]

always @ (posedge clk_153)
begin
 if (reset)
start_reading <= 1'b0 ;
else
   begin
      if(condition1)                           // once this condition occur start_reading is always high
        start_reading <= 1'b1 ;
   end
end

always @ (posedge clk_102)
begin
 if (reset)
    read/_en <= 1'b0 ;
else
   begin
      if(start_reading)                           // once this condition occur start_reading is always high
        read_en <= 1'b1 ;
   end
end

does start reading need cdc as start_reading signal is high always once condition is executed

 

[dpaul]

I would say it depends how timing critical is the setting of read_en <= 1'b1 in your design and how frequently condition1 is toggling.
It is always safe and good coding style to sample start_reading twice using clk_102 before using it in the if(start_reading) part.

 

[achaleus]

I would say it depends how timing critical is the setting of read_en <= 1'b1 in your design and how frequently condition1 is toggling.
It is always safe and good coding style to sample start_reading twice using clk_102 before using it in the if(start_reading) part.

Even if condition is changing start_reading is always high irrespective of condition after initial assignment

 

[ThisIsNotSam]

I have used this style on a lot of ICs. It works... but you have to be sure that the signal is really always stable before sampled in the other domain. That includes making sure someone else is not going to use the design/product in some unpredictable way that breaks the assumption.

 

[dpaul]

Even if condition is changing start_reading is always high irrespective of condition after initial assignment

Yeah I had missed that. Once condition1 occurs, only the reset can change the value of start_reading.
Post#4 is a better answer and I have similar opinion.