Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CDC for constant signal

Status
Not open for further replies.

achaleus

Member level 5
Joined
Dec 21, 2012
Messages
85
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Location
Bangalore
Activity points
1,866
Code:
always @ (posedge clk_153)
begin
 if (reset)
start_reading <= 1'b0 ;
else
   begin
      if(condition1)                           // once this condition occur start_reading is always high
        start_reading <= 1'b1 ;
   end
end

always @ (posedge clk_102)
begin
 if (reset)
    read/_en <= 1'b0 ;
else
   begin
      if(start_reading)                           // once this condition occur start_reading is always high
        read_en <= 1'b1 ;
   end
end

does start reading need cdc as start_reading signal is high always once condition is executed
 

dpaul

Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,559
Helped
310
Reputation
620
Reaction score
310
Trophy points
1,373
Location
Germany
Activity points
11,556
I would say it depends how timing critical is the setting of read_en <= 1'b1 in your design and how frequently condition1 is toggling.
It is always safe and good coding style to sample start_reading twice using clk_102 before using it in the if(start_reading) part.
 

achaleus

Member level 5
Joined
Dec 21, 2012
Messages
85
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Location
Bangalore
Activity points
1,866
I would say it depends how timing critical is the setting of read_en <= 1'b1 in your design and how frequently condition1 is toggling.
It is always safe and good coding style to sample start_reading twice using clk_102 before using it in the if(start_reading) part.

Even if condition is changing start_reading is always high irrespective of condition after initial assignment
 

ThisIsNotSam

Advanced Member level 5
Joined
Apr 6, 2016
Messages
2,208
Helped
383
Reputation
766
Reaction score
397
Trophy points
83
Activity points
11,338
I have used this style on a lot of ICs. It works... but you have to be sure that the signal is really always stable before sampled in the other domain. That includes making sure someone else is not going to use the design/product in some unpredictable way that breaks the assumption.
 

dpaul

Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,559
Helped
310
Reputation
620
Reaction score
310
Trophy points
1,373
Location
Germany
Activity points
11,556
Even if condition is changing start_reading is always high irrespective of condition after initial assignment
Yeah I had missed that. Once condition1 occurs, only the reset can change the value of start_reading.
Post#4 is a better answer and I have similar opinion.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top