How can I monitor a signal in post synthesis .v file

[achaleus]

Hello everyone,
I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast and I unable to add particular set of signals to the waveform window(I am adding all signals to the wave window) and its taking days for 1/10th of the simulation. It is difficult to find out the present value of my_signal.

My question is how can I monitor this hierarchical signal. gives you

if I use
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration );
or
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration[15:0] );
giving
Unresolved reference to 'UserModuleTop' in PicoSim.FPGA.UserWrapper.UserModuleTop.

Vinay

 

[dpaul]

Yes, would be quite difficult with the netlist.

I don't know if this is an effective solution or there might be better ones...
Bring out the signal to be monitored on the top level interface in the RTL, re-generate the netlist and the re-sim!

 

[achaleus]

Yes, would be quite difficult with the netlist.

I don't know if this is an effective solution or there might be better ones...
Bring out the signal to be monitored on the top level interface in the RTL, re-generate the netlist and the re-sim!

I thought the same and kept it as my final option...
thank you dpaul

 

[ads-ee]

Don't know if this is the situation in this particular case, but if the node you want to observe is not a FF then you will probably need to use a preserve attribute on it. This is less likely to affect timing and placement of a design and can also be left in the design, to avoid causing a subsequent mismatch due to code changes.

FFs on the otherhand should exist in a design. To help find them you can label the in your code

 

[achaleus]

Thank you dpaul and ads-ee for solutions. I used keep = TRUE attribute and pinned to the top level in the hierarchy.
and used $monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.my_iteration1 ); but I got
Unresolved reference to 'my_iteration1' in PicoSim.FPGA.UserWrapper.UserModule.my_iteration1.

I declared all those as wires and timing is not an issue as I want to check post synth simulation for functional behavior of my design.

any help or idea will be greatly appreciated

 

[ads-ee]

keep only works on individual nets afaik it does not apply to levels of hierarchy.
e.g.: (* keep = "true" *) wire signal_name;

FYI, sorry about misdirecting you to use preserve. I usually have to check which one applies to FFs and wires as I rarely use these attributes.

 

[achaleus]

Hello ads-ee (* KEEP = "TRUE" *) works for hierarchy also.. though I have taken that signal top to the hierarchy and kept as output.. but it is giving error as Unresolved reference.