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Recent content by abhi_123

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    Magma & unix (unix cmds in magma)

    You will have to invoke the mantle prompt to run the Magma commands for Unix. But if you wanna run commands such as Copy paste move, u will have to do so in ur Enviornment settings at Server. Added after 4 seconds: You will have to invoke the mantle prompt to run the Magma commands for Unix...
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    semi-custom /full custom

    This def by mani is close.
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    which process do you use now?

    CMOS
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    Analog Layout Considerations for 90nm!

    Hi All, Can any1 plz suggest me some specific Analog layout practices for 90nm and below.You know stuff like what more to take care at 90 and 65nm. I will be greatful for any pdf's .. web links.. Thanks in advance, Regards, Abhi
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    Info about flash ADC design in 150nm technology

    Hi All, I need to design a 4 bit Flash ADC in 150nm technology. Can someone suggest me some basic books/docs/ieee papers/web links.. to first get a basic understanding of design. Thanks in advance , Regards, Abhi
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    what's the DIBL stand for?

    Read either Weste or Kang for the concept behind "Drain induced Barrier Lowering " . Regards, Abhi
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    Magma Timing Issue with calculation of latency values !!

    magma io latency Hi All !! I am using config timing adjust latency to model source latency in my design.I have a multiple clock design. On the basis of this it calculates certain latency values (best : XXXX worst:XXXX). My query is on what basis are these values calculated? What is the...
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    Links to some introductory books about PLL

    pll book required Book By Ronal Best is available on the board also. Just look through the Upload/Download section. Regards, Abhi
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    Analog circuit design tool

    Cadence n HSPICE Avants
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    What do we mean by IO Latency in PnR Flow ?

    IO Latency What do we mean by IO Latency in PnR Flow. How is it different from Source and Network Latency.
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    What is a good core utilization percent ?

    Core utilization Hey Guys, Can you suggest what is the maximum limit is to Total utilisation. I mean which design one prefers a Standard design having 85% utilisation or a design having 95% utilisation. Thanks uin advance
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    Looking for materials on die size estimation in digital core

    die size estimation Let Total Cell Area be ‘X’ (which is known to us) Let Total Core Area be ‘Y’ Now Decide upon the Final Utilization of Core area You want, say 85 % To leave margin for Routing Resources and other optimization, take Utilization as 65% - 75 % Now X = 0.75 * Y So Y can be calculated
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    How to cancel charge injection??

    I think the concept n remedy o charge injection is explained beautifully in Analo Integrated Circuits-Ken n Martin ; the book is available on the board. so, just look up.
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    pls clear my doubts on memory design

    Hi, Here are my Answers: 1.Don't adjust the width in the model file . c the SPICE file provided the fab generally has a no. of combinations of transistor widths that can be manufactured, they give sumthg like Wmax for a L. n anyways not all your transistor in SRAM will have same W so, changing...
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    What is the use of select layer in layout of circuits?

    Select layer in layout The Select region defines what kind of diffusion it has. generally tools have Active defined unless u surround it with a select it has no way of knowing what kind of MOS u intend to make.
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