what's the DIBL stand for?

[rock_zhu]

anyone can give me a definite explanation? i don't know why the Vt is reduced with the Vds increasing.thx!

 

[jcpu]

Hello:

"drain induced barrier lowering"
a very typical short channel effect,
knowledge could be found in websites like:
www.stanford.edu/class/ee316/MOSFET_Handout5.pdf
ece-www.colorado.edu/~bart/book/book/chapter7/ch7_7.htm
www.cs.ucl.ac.uk/staff/d.quercia/projects/vlsi/talk.ppt

basically for long channel device, Ids is solely controlled by Vgs,
while for very short channel devices, raising drain voltage
can also affect the electric field distribution under gate oxide,
and thus reducing the Vth....increasing the leakage current.

Hope that helps

 

[Willt]

Hi friend,

DIBL stands for drain-induced barrier lowering.

Considering a NMOS, when Vds increases with fixed Vgs, the depth of depletion region across the drain (n+) and the bulk (p+ fixed at Vss) increases [more reverse-biased]. As a result, less region across a MOS is needed to be depleted, and then form a channel.

Vt threshold voltage is the minimum voltage needed to be applied to the gate in order to form a channel in the MOS. To form a channel, the region across a MOS is needed to be first depleted by increasing the gate voltage, then a channel is formed if we continue to do so.

In conclusion, if we increase Vds, less region across a MOS is needed to be depleted and thus less gate voltage is required to form a channel across a MOS.

Please advise me if I have made any mistake ~

Will

 

[eezou]

DIBL is drain induced barrier lowering.
You can learn from semiconductor device physics

 

[rock_zhu]

Thanks for your enthusiastic help.

 

[abhi_123]

Read either Weste or Kang for the concept behind "Drain induced Barrier Lowering " .

Regards,
Abhi

 

[manissri]

DIBL stands for drain induced barried lowering.
actually when u increase ur drain voltage of ur mos without increasing the gate voltage then due to voltage difference the barrier of source will fall and there is a current flow in the mos without increasing the gate voltage.
it is some sort of leakage current.
hope this helps u.
regards

Added after 2 minutes:

DIBL stands for drain induced barried lowering.
actually when u increase ur drain voltage of ur mos without increasing the gate voltage then due to voltage difference the barrier of source will fall and there is a current flow in the mos without increasing the gate voltage.
it is some sort of leakage current.
hope this helps u.
regards

Added after 3 minutes:

DIBL stands for drain induced barried lowering.
actually when u increase ur drain voltage of ur mos without increasing the gate voltage then due to voltage difference the barrier of source will fall and there is a current flow in the mos without increasing the gate voltage.
it is some sort of leakage current.
hope this helps u.
regards