XILINX AXI 128bit

[Zerox100]

Dear my friends,

I have read the AXI4 standard from xilinx. In this manaul it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to use AXI in 64 or 128bit wide. Does anybody know about this issue?

THANKS

 

[TrickyDicky]

What exactly is the problem? The axi width has no effect on behaviour, just more data can be transferred per clock

 

[dpaul]

use AXI4 as a ip core for ZYNQ

There should be some generic to change such as DATA_BUS_WIDTH or something similar. Find that out and change it. See the configurable parameters of the IP core.

 

[Zerox100]

There should be some generic to change such as DATA_BUS_WIDTH or something similar. Find that out and change it. See the configurable parameters of the IP core.

I did it. But it does not work.

 

[Zerox100]

Anybody could provide a detail guide?

 

[dpaul]

Can you post the link to the IP's Xilinx user guide that you are using?

I did it. But it does not work.
What do you see in simulation after you change the bus width?