XILINX AXI 128bit?

[HarperWyatt]

Dear my friends,

I have read the AXI4 standard from xilinx. In this manaul it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to use AXI in 64 or 128bit wide. Does anybody know about this issue?

THANKS

 

[TrickyDicky]

Are you talking about AXI4, AXI4L or AXI4S. AXI4L is typically 32 bits as it us usually used for control registers. But AXI4 and AXI4S can be a variety of widths.

 

[HarperWyatt]

Dear my friends,

I have read the AXI4 standard from xilinx. In this manau
VidMate Mobdro

l it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to use AXI in 64 or 128bit wide. Does anybody know about this issue?

THANKS

issue got solvedd

 

[elwishseven]

AXI, which means Advanced eXtensible Interface, is an interface protocol defined by ARM as par of the AMBA (Advanced Microcontroller Bus Architecture) standard. The AXI3/AXI4 specification are freely-available on the ARM website (link) so I encourage anybody who is interested to download it.