Zerox100
Full Member level 6
Dear my friends,
I have read the AXI4 standard from xilinx. In this manaul it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to use AXI in 64 or 128bit wide. Does anybody know about this issue?
THANKS
I have read the AXI4 standard from xilinx. In this manaul it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to use AXI in 64 or 128bit wide. Does anybody know about this issue?
THANKS