why ?the large difference between dc and synplify?

[mic_huhu]

Hi, all

I am confused by this: when I synthesis a module with synplify ,there is no time violations.however, something happens in dc, it reports some path must three clock period. why?

thanks.

JOhnny

 

[nand_gates]

I think the reason for this is Synplify does logic optimization irrespective of
timing constraints. Where as Synopsis tool does timing driven optimization.
It does not do optimization if the rtl meets timings. So I think you need to check
for ur timing constraints correctness.
Other thing you can do is compare both the netlists! This may give you some
clue about what is happening.

 

[eda_wiz]

Sometime back I synthesised my RTL with Synplify ASIC and Design Compiler... Synplify easily meets the tming constraints.. but DC just met the constraints I have given.. i wondered why a verstaile tool like DC is struggling to meet timing when synplify easily meets timing.......

But when I check the area synplify area was approximately 2.5 times DC area..


rgds

 

[mic_huhu]

Thanks.

However, I am confused by the DC report about some paths only two or and and gate . does the path must three clock ? (the path is a control signal to a register, I think it is wrong ) . I don't know what is happen?

Johnny

 

[jinruan]

if your RTL code is ok ,
set timing exception to the path in your constraints.

 

[haoboy]

there must be something wrong in ur code or DC setting.

 

[vibhute_r_p]

I feel these things are typically code dependent. However the fact is that every tool has its own optimisation algorithm. these alogorithms are sensitive to constrains you provide. even if you take he default constrains in tools ..these constrints very from tool to tool. The time taken by tool to optimize is directly proportional to no of constraints...

 

[gogogo]

different software has different ideas!
in my opnion, DC is much stronger than synplify
so you should take DC as standard