mic_huhu
Member level 3
Hi, all
I am confused by this: when I synthesis a module with synplify ,there is no time violations.however, something happens in dc, it reports some path must three clock period. why?
thanks.
JOhnny
I am confused by this: when I synthesis a module with synplify ,there is no time violations.however, something happens in dc, it reports some path must three clock period. why?
thanks.
JOhnny