Use interface signals as inout in systemverilog

[antlhem]

What is the proper way to use same signals of an interface as input or output? I am aware that the way i am doing it, could end up with Xs since there are no restrictions in the use of the signals from the interface.

So what is the way to do this using the modports?

Code, Use signals as input or input or output of the same interface

interface tx_bfm();
  logic clk;
  logic ch;
  logic [7:0] data;
 
  modport tx_mst(output clk, ch, data);
  modport tx_slv(input clk, ch, output data);
 
  always @(posedge clk)
    if(ch)
      data = data + 1;
    else
      data = 0;
 
endinterface
 
interface rx_bfm();
  logic clk;
  logic ch;
  logic [7:0] data;
  bit [7:0] data_q [$];
 
  modport rx_mst(output clk, ch, input data);
  modport rx_slv(input clk, ch, data);
 
  always @(posedge clk)
    data_q.push_back(data);
endinterface
 
module tb;
 
  bit clk;
 
  /** Clk signal **/
  always #1 clk = ~clk;
 
  /** Instance for Interfaces **/
  tx_bfm tx_bfm0();
  rx_bfm rx_bfm0();
 
  /** Using tx_bfm as master without modport**/
  /*
  assign tx_bfm0.clk = clk;
  assign rx_bfm0.clk = tx_bfm0.clk;
  assign rx_bfm0.ch = tx_bfm0.ch;
  */
 
  /** Using rx_bfm as master without modport**/
  assign rx_bfm0.clk = clk;
  assign tx_bfm0.clk = rx_bfm0.clk;
  assign tx_bfm0.ch = rx_bfm0.ch;
 
  /** Trying to use modports for tx_bfm **/
  //tx_bfm.tx_mst tx_bfm_mst0();//
 
  initial begin
    $display("::-- Testing --::");
 
    /** Trying to use modports for tx_bfm **/
    //tx_bfm_mst0.clk = clk;
    //tx_bfm_mst0.ch = 1;
 
    #10 $finish;
  end
endmodule