I need help in systemverilog

[dfgt]

I am using Zybo, I assign "SI" to write to a button, when I press it, all the data is filled the same, it does not give me time to collect one data and another. So, once I press "SI" the DIR led turns off and the "DOR" led turns on and the "SO" button reads only one data.
How can I Improve my syntax?

module fifito(
        input logic clk,
        input logic MR, //RESET
        input logic [3:0]D, //DATA IN
        input logic SO,//read
        input logic SI, //write
//        input logic TSC,
        output logic [3:0]Q, // DATA OUT
        output logic DIR,//Empty
        output logic DOR //Full
    );
    logic [15:0][3:0]buffer;
    logic [3:0] SO_ptr,SI_ptr;
    logic [15:0] estado;
   
    assign     DIR = (estado == 0);
    assign     DOR = (estado == 15);
   
    always@(posedge clk or posedge MR)
    begin
        if (MR)
        begin
            Q <= 0;
            buffer <= 0;
            estado <= 0;
            SO_ptr <= 0;
            SI_ptr <= 0;
        end
        else
        begin
        Q <= Q;
        buffer[SI_ptr] <= buffer[SI_ptr];
        SO_ptr <= SO_ptr;
        SI_ptr <= SI_ptr;
        if (SO && !DIR)
        begin
            Q <= buffer [SO_ptr][3:0];
            estado [SO_ptr] <= 1'b0;
            SO_ptr <= SO_ptr + 1;
        end
        else if (SI && !DOR)
        begin
            buffer [SI_ptr] <= {D};
            estado [SI_ptr] <= 1'b1;
            SI_ptr <= SI_ptr + 1;
        end
    end
end
endmodule

module div(input logic clk, MR,
           output logic clk1);
           reg [125:0] count;
           always_ff @(posedge clk)
           count <= count + 1;
           assign clk1 = count[125];
endmodule

 

[FvM]

I take a look at your clock "divider". The clock period is something like 10^22 years with 50 MHz input clock, if synthesized correctly. But fortunately you don't need to wait til eternity because clk1 isn't yet used.

Using buttons to set SI and SO simply doesn't work without debouncing logic and generating a single clock wide pulse per button press. Better test your design in a simulator.