Problem with using FIFO with Block Rams as memory type

[Zhane]

I created a 2 independent clock FIFO with Block Rams as memory type using the Xilinx CoreGen.

I set it up for width: 5 and depth: 65k. The total capacity should be 320k bits

but my FIFO output full signal seems to go active even before I manage to write in 32kbits of data

I have nothing else that uses the blockram on my implementation


does anyone have any idea where did I go wrong?

 

[saikat]

Re: Block Rams

How did you fill up the FIFO?

You should use a signal vector of 5 bit width as an entry and the no. of such entry should be maximum of 65k-1.

even your data is only 2 or 3 bit wide, you have to pad up 0 and make it a 5 bit wide entry for the FIFO.

The clocks of the FIFO should run continuously and read/write operations should be controlled by chip-enable/port-enable signals.

 

[Zhane]

Re: Block Rams

I did make sure the thing I send in is only 5bit.

my clocks are running continuously also

and my read and write signals are controlled by read and write enable ports.

however I dont think I sent in more than 65k-1 5bits..cause the output I got from it is only 32kbits the most...and the full signal came up.



can I read the FIFO when it is writing?

 

[salma ali bakr]

Re: Block Rams

don't you have two independent read and write signals ??
what's the problem then in reading from the FIFO while writing to it??

 

[Zhane]

Re: Block Rams

don't you have two independent read and write signals ??
what's the problem then in reading from the FIFO while writing to it??

ya
juz wondering if this is the problem
cause.. i cant think of any other reason y i cant use the entire FIFO

 

[salma ali bakr]

Re: Block Rams

are you using the same clock frequency for reading and writing ??

 

[Zhane]

Re: Block Rams

are you using the same clock frequency for reading and writing ??

different
the clock source is different also

 

[salma ali bakr]

Re: Block Rams

are you sure the ram starts empty??
how is your full flag described??

 

[Zhane]

Re: Block Rams

are you sure the ram starts empty??
how is your full flag described??

I download a fresh copy of the stuffs into my FPGA... doesnt this resets my ram to the empty stage? I did trigger the reset for fifo too...


I just output my fifo_full to an led on my fpga... and the led lits up whenever fifo_full is 1

 

[salma ali bakr]

Re: Block Rams

i mean, how do you test if your FIFO is full or empty?? the code ??

 

[Zhane]

Re: Block Rams

i mean, how do you test if your FIFO is full or empty?? the code ??

the fifo component
as an output signal fifo_full which goes active when it is full

i used this to to see if it is full

 

[salma ali bakr]

Re: Block Rams

aha...ok

this is very strange..that it's full before it's actually full..!!

would you like me to check your design ?? I can do that later today

 

[Zhane]

Re: Block Rams

aha...ok

this is very strange..that it's full before it's actually full..!!

would you like me to check your design ?? I can do that later today

how should I let you check?
email you the code?

 

[salma ali bakr]

Re: Block Rams

yah...
just send me the files needed in a PM...

 

[Zhane]

Block Rams

sent

 

[ihearme]

Block Rams

My 2 cents...
In Xilinx FIFO Generator, there's a "Full Flag Reset Value" on page 3 where you select to enable/disable flags. How is it?

 

[saikat]

Re: Block Rams

Watch your write control signal. This should be asserted for one clock cycle only.

If this is asserted for multiple clock cycle, then same data will repeatedly go inside the FIFO.

 

[Zhane]

Re: Block Rams

I had the clock on for a few clocks
but every clock the datain changes....so i actually wrote in diff data

and my output came out as expected.



the full flag reset...what does it does?

 

[ihearme]

Re: Block Rams

The reset value of the full flag can be set by LogiCore FIFO Generator. (see attached pic)
The FIFO full flag can come up from reset as "full" even though you have no data in it.

I'm not sure why they have this feature. I had this bug once.

 

[satyakumar]

Re: Block Rams

In fifo generation if we use distributed RAM does it going to impact the area as well?
I know that it effects timing.