Asynchronous, Asymmetrical FIFO using logiCORE FIFO Generator in Vivado

[hassannriaz]

As a part of project I am required to generate a 192-bit to 128-bit Asynchronous FIFO in Vivado. Now I am presented with two options:
i) Write such a FIFO from scratch
ii) Use a possible combination of Vivado logiCORE FIFO generator
If there are any possibilities in FIFO generator that would be the easier way out, if not, are there any good resources to start writing an Asynchronous and Asymmetrical FIFO?

 

[kaz1]

If it is to show work to your professor then follow his expectations before he gets angry. Otherwise use fifo generator so you don't re-invent the wheel.

 

[hassannriaz]

If it is to show work to your professor then follow his expectations before he gets angry. Otherwise use fifo generator so you don't re-invent the wheel.

No it is not to be shown to the professor, it is just an intermediate part of a long term project. The problem remains, I am unable to find a possible combination in FIFO generator to generate a 192 to 128 bit FIFO.

 

[ads-ee]

You can use a logiCORE 192 to 192 asynchronous FIFO and add a wrapper that converts the 192-bit output to a 128-bit output.
The wrapper presents a 128-bits of the 192-bits when you "read" the wrapper FIFO. The next read will output the last 64-bits (out of the first 192-bit read) and will read out another 192-bits, returning only 64-bits (64-bit+64-bit 128-bits). The third FIFO read will return the remainder 128-bits (with no logiCORE read).

You will have to continuously keep track of writing two and reading 3 to generate the correct empty flag.

 

[kaz1]

You can use a logiCORE 192 to 192 asynchronous FIFO and add a wrapper that converts the 192-bit output to a 128-bit output.
The wrapper presents a 128-bits of the 192-bits when you "read" the wrapper FIFO. The next read will output the last 64-bits (out of the first 192-bit read) and will read out another 192-bits, returning only 64-bits (64-bit+64-bit 128-bits). The third FIFO read will return the remainder 128-bits (with no logiCORE read).

You will have to continuously keep track of writing two and reading 3 to generate the correct empty flag.

That is good idea.
The alternative is 128/128 fifo with three states logic at input side:
s0: write 128 bits out of 192 bits, save other 64 bits
s1: wait for next 192 word, take 64 bits and concatenate with above 64bits
s2: write total of concatenated 128 bits to fifo
s0: write next 128 bits and so on.