STA timing closure for asynchronous FIFO

[promach]

I have implemented an asynchronous FIFO

However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.

Both read_clk and write_clk are having the same clock frequency.

Could anyone advise ?

 

[std_match]

1. Don't use the "simplify" full/empty options
2. Set all clock domain crossing signals as "false paths".