Zhane
Member level 5
I created a 2 independent clock FIFO with Block Rams as memory type using the Xilinx CoreGen.
I set it up for width: 5 and depth: 65k. The total capacity should be 320k bits
but my FIFO output full signal seems to go active even before I manage to write in 32kbits of data
I have nothing else that uses the blockram on my implementation
does anyone have any idea where did I go wrong?
I set it up for width: 5 and depth: 65k. The total capacity should be 320k bits
but my FIFO output full signal seems to go active even before I manage to write in 32kbits of data
I have nothing else that uses the blockram on my implementation
does anyone have any idea where did I go wrong?