Problem with simulating PAR model in Modelsim

[snake0204]

Hi everyone,

When I try to simulate a PAR model of my design it is not working. I am using xilinx ISE to do place and route and modelsim to simulate the model. I constrained my design to run at 100mhs that is placed a global constraint on my block. Here is the code for my simple adder circuit. All the input signals form IO pads are registered at +ve clk edge. I am new to this area and just started exploring things.

The start signal is made high on a +ve edge to start the block and mode low on the next +ve clock edge.

Any help please Thanks!!!

-- This process register all the input data and control signals
IPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
START_REG <= '0';
D1 <= (OTHERS => '0');
D2 <= (OTHERS => '0');
ELSE
START_REG <= START;
D1 <= DATA1;
D2 <= DATA2;
END IF;
END IF;
END PROCESS;

--This is the finite state machine process that controls the whole block
PPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
STATE <= IDLE;
ELSE
CASE STATE IS
WHEN IDLE =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
WHEN ADD =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;

--Fsm outputs
OUP: PROCESS(STATE)
BEGIN
ADD_EN <= '0';
CASE STATE IS
WHEN IDLE =>
NULL;
WHEN ADD =>
ADD_EN <= '1';
END CASE;
END PROCESS;

--adder circuit
REG_PROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
DATA_OUT_REG <= (OTHERS => '0');
ELSIF ADD_EN = '1' THEN
DATA_OUT_REG <= D1 + D2;
END IF;
END IF;
END PROCESS;

 

[banjo]

Simulating PAR model

Why are you trying to simulate the PAR model? Are you having problems with the actual design?

Typically, we never attempt to simulate the PAR model. Instead, we do functional simulation on the HDL code itself and then rely on timing constraints to insure the FPGA will run at speed. (We do not simulate PAR models, because they run too slow and take too much effort to get working.)

If you have not done functional simulation, I would start with that. In Xilinx designs, we have to include "glbl.v" to get the designs to come out of reset. We also need to include several of the Xilinx simulation libraries like the unisim and simprim libraries. Get functional simulation working first before tackling simulating PAR models.
Post back exactly what the state of the signals are: They they stuck at high -Z, at '1' or '0' or at unknown, aka 'X'.

 

[snake0204]

Re: Simulating PAR model

Thanks for the reply....

I don't have any problems with my functional simulation it works fine. I am trying to simulate the PAR model just to make sure every thing works.

I included all the simprim unisim simulation libraries form Xilinx thats not a big problem the Xilinx ISE tool does that for me.

please look at my other post
where I posted a simulation wave figure, there is a FSM in my design which switches state when there is a start signal on +ve clk edge, you can see the start signal going high on a +ve edge and drop on the next +ve edge but the state is remaining the same.

IF CLK' EVENT AND CLK = '1' THEN
IF START = '1' THEN
STATE <= NEXT_STATE;
ELSE
STATE <= CURRENT_STATE;
END IF;
END IF;

The PAR simulation works fine when i don't drop the start signal to low at the next edge.