snake0204
Newbie level 5
Hi everyone,
When I try to simulate a PAR model of my design it is not working. I am using xilinx ISE to do place and route and modelsim to simulate the model. I constrained my design to run at 100mhs that is placed a global constraint on my block. Here is the code for my simple adder circuit. All the input signals form IO pads are registered at +ve clk edge. I am new to this area and just started exploring things.
The start signal is made high on a +ve edge to start the block and mode low on the next +ve clock edge.
Any help please Thanks!!!
-- This process register all the input data and control signals
IPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
START_REG <= '0';
D1 <= (OTHERS => '0');
D2 <= (OTHERS => '0');
ELSE
START_REG <= START;
D1 <= DATA1;
D2 <= DATA2;
END IF;
END IF;
END PROCESS;
--This is the finite state machine process that controls the whole block
PPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
STATE <= IDLE;
ELSE
CASE STATE IS
WHEN IDLE =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
WHEN ADD =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
--Fsm outputs
OUP: PROCESS(STATE)
BEGIN
ADD_EN <= '0';
CASE STATE IS
WHEN IDLE =>
NULL;
WHEN ADD =>
ADD_EN <= '1';
END CASE;
END PROCESS;
--adder circuit
REG_PROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
DATA_OUT_REG <= (OTHERS => '0');
ELSIF ADD_EN = '1' THEN
DATA_OUT_REG <= D1 + D2;
END IF;
END IF;
END PROCESS;
When I try to simulate a PAR model of my design it is not working. I am using xilinx ISE to do place and route and modelsim to simulate the model. I constrained my design to run at 100mhs that is placed a global constraint on my block. Here is the code for my simple adder circuit. All the input signals form IO pads are registered at +ve clk edge. I am new to this area and just started exploring things.
The start signal is made high on a +ve edge to start the block and mode low on the next +ve clock edge.
Any help please Thanks!!!
-- This process register all the input data and control signals
IPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
START_REG <= '0';
D1 <= (OTHERS => '0');
D2 <= (OTHERS => '0');
ELSE
START_REG <= START;
D1 <= DATA1;
D2 <= DATA2;
END IF;
END IF;
END PROCESS;
--This is the finite state machine process that controls the whole block
PPROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
STATE <= IDLE;
ELSE
CASE STATE IS
WHEN IDLE =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
WHEN ADD =>
IF START_REG = '1' THEN
STATE <= ADD;
ELSE
STATE <= IDLE;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
--Fsm outputs
OUP: PROCESS(STATE)
BEGIN
ADD_EN <= '0';
CASE STATE IS
WHEN IDLE =>
NULL;
WHEN ADD =>
ADD_EN <= '1';
END CASE;
END PROCESS;
--adder circuit
REG_PROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK = '1' THEN
IF RST = '0' THEN
DATA_OUT_REG <= (OTHERS => '0');
ELSIF ADD_EN = '1' THEN
DATA_OUT_REG <= D1 + D2;
END IF;
END IF;
END PROCESS;