problem with instantiation in VHDL

[rg350dxlover]

You have to make 10 outputs, and each one of them get a value after a certain amount of time:
when "0000" => outp1HZ<='1';
when "0001" => outp2Hz<='1';outp1Hz <= '0';
etc etc.

So if I continue the above example, for outp3Hz, is this right?
when "0010" => outp3Hz <= '1'; outp1Hz <= '0'; outp2Hz <= '0';

 

[TrickyDicky]

if one of the outputs is '1', you have to make sure all of the other outputs are '0';