problem ON ANALOG CMOS circuit!

[nivico]

min w 1.2u cmos

I am a university student from China.
I am doing some design of cmos analog opamp using TANNER EDA,and was confused by the W/L;I am using orbtn12/orbtp12 tech.
i appreciate your help that you could send me a finished design of a simple design,
t-spice file,layout even better.
E-mail: ldbqyy@sohu.com

 

[noiseless]

cmos 1.25um process model file

Read your textbook patiently. I don't understand why you said you do not understand W/L!

 

[amarnath]

tspice file of simple current mirror

hi sohu,just try designing a simple op-amp ,possibly with a current load.u are suppose given specifications for icmr(min), icmr(max),power,gain.then u can write down a few equations and solve them for the various w/l ratios of the transistors.i advise u to refer to allen and holberg for this design.if u still have any doubts please feel free to ask them in this forum.but first put in your effort to understand things.

regards
amarnath

 

[nivico]

mcnc 1.25um cmos parameters

Here is the t-spice file I just simulated,it is about a differencial amp.please help me check the file,or adjust the paramenter,thanks a lot!
* SPICE netlist written by S-Edit Win32 8.10
* Written on May 29, 2005 at 22:32:21
.include "E:\Tanner\TSpice81\models\ml2_125.md"
* Waveform probing commands
.probe
.options probefilename="File0.dat"
+ probesdbfile="E:\Tanner\diff\3\File0.sdb"
+ probetopmodule="3"
* Main circuit: 3
M1 VOUT N12 VCC VCC PMOS L=1.2u W=6.6u
M4 N11 N12 VCC VCC PMOS L=1.2u W=6.6u
M2 N11 V+ N4 N4 NMOS L=1.2u W=3.6u
M3 VOUT V- N4 N4 NMOS L=1.2u W=3.6u
M5 N4 V2 VSS VSS NMOS L=2.4u W=1.8u
v6 VCC Gnd 12.0
v9 VSS Gnd -12.0
v10 V2 Gnd -3.0
v7 N12 Gnd 9.0
v8 V+ Gnd 0.0
v11 V- Gnd 1.0
* End of main circuit: 3
.dc lin source V11 -2 2 0.01
*lin v10 -2.5 -3.5 .2
*lin source v7 9.29 9.31 .01
.print dc V(VOUT) V(N11,VOUT) V(N11) v(v2,vss) v(vcc,vout)
* v(vout n11) V(N4) ID(M5)

 

[yorande]

vmax=177269

what do you want other to check???
if you are not sure for the circuit's performance parameters, there is nothing to check!!!
get a clear map of what you wanna achieve before you design your circuits...
If you just practise, then simulate some circuits in textbooks helps a lot..

 

[layes2]

cmos 1.25umnominal parameters

nerver use that tanner cadence is better

 

[qutang]

i think pspice is more suitable than tanner

 

[jotamario]

Have you seen the model file: ml2_125.md?

You need to know the parameters in this model and then W and L.

 

[dog1357]

u need to know the process before you step into parameters like W or L.
basically need to find Kn Kp, then Vt Vn, then goes to gm, bias current and so on.
For layout, u can try your self, poly student can aslo do quite well if they work hard

 

[feel_on_on]

HSPICE is better !

 

[nivico]

It costs to use Cadence,thanks a lot for your reply.during the time, I did much simulation,and got a much better result,the CMRR is 81dB,and 3dB frequence is about 3Mhz ,here is the spice file.we can have more discuse on this topic.

Added after 52 seconds:

* SPICE netlist written by S-Edit Win32 10.00
* Written on Jun 16, 2005 at 12:36:59
.include "..\ml2_125.md"

* Waveform probing commands
.probe
.options probefilename="new_attitude"
+ probesdbfile="H:\diff\8\new_attitude.sdb"
+ probetopmodule="new_attitude"

* Main circuit: new_attitude
M1 N7 IN2 N2 N2 NMOS L=18u W=1.8u
M2 N8 in1 N2 N2 NMOS L=18u W=1.8u
M3 N2 N3 vss vss NMOS L=15u W=1.8u
M4 N8 N7 Vdd Vdd PMOS L=36u W=1.8u
M5 N7 N7 Vdd Vdd PMOS L=36u W=1.8u
v6 Gnd vss 5
v7 Vdd Gnd 5
*v8 IN1 Gnd vol
v9 N3 vss 3
*v10 IN2 Gnd 0
*End of main circuit: new_attitude

Added after 4 minutes:


********************************************************
**
** MCNC 1.25um CMOS Process
** Nominal Level 2 MOSFET Parameters
** 2/26/87
**
********************************************************

.model nmos nmos
+ Level=2 Ld=0.0u Tox=225.00E-10
+ Nsub=1.066E+16 Vto=0.622490 Kp=6.326640E-05
+ Gamma=.639243 Phi=0.31 Uo=1215.74
+ Uexp=4.612355E-2 Ucrit=174667 Delta=0.0
+ Vmax=177269 Xj=.9u Lambda=0.0
+ Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10
+ Tpg=1.000 Rsh=60 Cgso=2.89E-10
+ Cgdo=2.89E-10 Cj=3.27E-04 Mj=1.067
+ Cjsw=1.74E-10 Mjsw=0.195

.model pmos pmos
+ Level=2 Ld=.03000u Tox=225.000E-10
+ Nsub=6.575441E+16 Vto=-0.63025 Kp=2.635440E-05
+ Gamma=0.618101 Phi=.541111 Uo=361.941
+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0
+ Vmax=63253.3 Xj=0.112799u Lambda=0.0
+ Nfs=1.668437E+11 Neff=0.64354 Nss=3.00E+10
+ Tpg=-1.00 Rsh=150 Cgso=3.35E-10
+ Cgdo=3.35E-10 Cj=4.75E-04 Mj=.341
+ Cjsw=2.23E-10 Mjsw=0.307

 

[Humungus]

I recommend you going to the basis!!!! Try to understand what you do!!!

Please read Cargo Cult Science by Richard Feynman and this would help you to understand what it is supposed to do a scientis/engineer.

Your amplifier is nonsense!! Your transistors are in extreme strong inversion. Never bias tail current source with a voltage. Just copy the bias current from another transistor. No way you can get 81dB of CMRR with that circuit!!! What you simulated is just the systematic CMRR. The random CMRR, which is given by transistor mismatches, will dominate.

REMEMBER: try to understand what you do!!!!

 

[muldersun]

From your netlist, I thinks it is only used to simulate.
Depend on your application,you should know the requestion, you need to trade off.
About OPAMP,you can read Allen's book first.

 

[nivico]

thnaks for your advice , it is true that i am a begginer,i also see the enhancement , i will go on ;i just posted the first stage of an amp . i can easily get the bias "v9 N3 vss 3" , i think the other transistor suply a voltage rather than copy the current as the ransistor can be different .i will finish the current mirror ,and i have a question "have you ever simulated the circuit "
i use the book of analysis and design of analog integrated circuit by Paul R. Gray , i will follow your advice to read Cargo Cult Science by Richard Feynman , if you really happy to help a beginner , please give me a example that i can simulate , and understand it exactly . thanks a lot for your reply !

Added after 12 minutes:

"So I have just one wish for you -- the good luck to be somewhere where you
are free to maintain the kind of integrity I have described, and where you
do not feel forced by a need to maintain your position in the organization,
or financial support, or so on, to lose your integrity. May you have that freedom"
--by Richard Feynman

i will remember , thanks !