[SOLVED] Convergence Problem with analogLib vpulse

[memoslw]

Hello,

I have a BGR circuit in schematic. Basically, I want to pull one of the nodes to vdd by utilising an analogLib vpulse connected to an analogLib switch. By this way, the node I want to control would be pulled high periodically and I can observe the circuit's behaviour (theoretically).

At first, I set up the vpulse and switch circuit separate from the BGR circuit I have, but both are residing in the same schematic. When I ran a transient analysis, I got an error (SPECTRE-16192) stating that no convergence achieved. The simulation log have given info about the nodes that had "Solutions too large", all these nodes are residing on my BGR circuit. I am listing info that might be useful below:

• I have previously done transient analysis on my BGR circuit without the vpulse and switch circuit, the circuit behaviour is as expected and simulation converges with no errors.
• My BGR circuit consists of transistors and resistors from a 22nm technology, but it also has an ideal amplifier from analogLib (vcvs).
• The amount of time for transient simulation to fail is somehow related to the period of the vpulse. Convergence error occurs as soon as one period of the vpulse passes.

I can give further details upon request. I would appreciate any help, information and/or suggestion, thank you all in advance.

 

[Dominik Przyborowski]

Seems you are forcing to ideal sources to fight each other. Without schematic/netlist or even the spectre log, it is hard to say anything more.

 

[dick_freebird]

Ideal switches can be too ideal as well. As a minimum, apply good
"on" and "off" resistance values and sane VON/VOFF (hysteresis
there can defeat DC solution, but I like some anyhow, using some
sort of startup circuit).

I have sometimes found switch behavior troublesome and used
a poly vccs to make the same function (basically a multiplier)
given proper control voltages (=0 -> "off", positive value = "on"
resistance scale factor, a minuscule "off" voltage can represent
leakage).

It would not be a terrible idea to put trivial resistors between any
two "ideal" elements. What is "trivial" depends on what you are
up to, but "trivial" can be determined by a sensitivity analysis or
toggled by using variables, to see outcomes.

 

[memoslw]

I have solved the issue. The problem was vcvs and vpulse being in the same schematic together. It might be a bug. I have changed the vcvs with an OPAMP I created, which solved the issue. I am using Virtuoso version ICADVM20.1-64b.14.

Thank you all for the help.