CMOS breakdown voltage

[goatmxj666]

Hello,

I am designing power amplifier, using 350nm CMOS process.

The supply voltage is 3.3V.

I have to concern the breakdown voltage, Vds.

Right now, my Vds is about 5.7V.

Of course, the breakdown voltage is chagned depending on the its width,

but I wonder how much the mosfet can withstand the VDS in generally.

 

[dick_freebird]

Breakdown is one thing, early degradation from hot carrier effects
is another (and tends to be the limiting factor for reliability, especially
if operation at low or room temp is the norm.

Now I would expect a short channel NMOS from a 3.3V technology
to be exhibiting some "drain curl" at or before 3.3V (onset of impact
ionization) and a pretty hard breakdown around 4V.

I might recommend the output switch / driver be cascoded with gate
to the +3.3, but this works better on RF SOI CMOS; there is no escaping
the MOSFET D-B breakdown (though that is probably "about 6-7V").

Foundries don't want to tell you about details like true breakdown
and what happens under a specific conditions-set as you approach it.
Because then you're going to try to approach it. So they set and then
insist to be followed, conservative (way-, or less so, is an unexplored
alley of corporate honesty and thoroughness).

And MOSFET models tend to still ignore breakdown and near-bkdn
behaviors altogether. Aside from maybe throwing some yips to the
output log. So spend some time looking at worst case crest voltages
terminal-to-terminal.