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If your design have macros, then if you dont floorplan the macros without giving routing space for interconnection between macros, it will create congestion.
Start the initial target utilization with 65%-70%.
Routing congestion can be due to:
1. High standard cell density in small area.
2. Placement of standard cells near macros.
3. High pin density on one edge of block.
4. Placing macros in the middle of floorplan.
yadavvlsi provides meaningful solution for your question.
Feeds behavior(crisscross),number of feeds matter and that also comes under IO pin density
Up to what extent over macros blockages are present and how many dedicated metal layers are available for signal routing apart power routing and clock routing
Not a good floorplan
Placement of complex cells in a design
Need to look at constraints also. During IO optimization tool does buffering so lot of cells sits at core area.
1.If your design had more number of aoi/oai cells you will see this congestion issue.
2. crisscross IO pin alignment is also a problem. (as Yadav said)
3.Module splitting.
there are so many mitigation plans to reduce the congestion if your overall or global congestion is under control.
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